Vendor: V-Trans Microelectronics Category: V-By-One

Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression

This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…

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Overview

This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.

This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMOS data plus 10 control signals (VSYNC, HSYNC, DE, and 7 user-defined signals).

At a maximum pixel rate of 170Mhz, LVDS data line speed is 1.19Gbps, providing a total maximum bandwidth of 11.9Gb/s (1.487Gbytes per second).

This IP can drive two (2) independent displays with resolution up to UXGA/Full HD (dual asynchronous input /output).

Key features

  • • Dual independent single link mode (can drive 2 separate displays with different resolution)
  • • 1P8M layout structure based on SMIC 40nm Logic LL 1P10M Salicide 1.1V/2.5V process.
  • • 1.1V/2.5V +/-10% supply voltage, -40/+125C
  • • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
  • • Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
  • • Input clock detector (self reset when missing clock)
  • • Spread-spectrum input clock support
  • (can be used in SS systems)
  • • Output Swing Control (2.5mA to 7mA programmable), PVT compensated
  • • Input clock detector (self reset when missing clock)
  • • Low leakage power-down mode <10uA
  • • Core cell area : [contact us] (I/Os included)
  • • Power consumption [contact us] @150Mhz
  • • Built-in power pads with ESD protection.
  • • Equivalent part : Thine’s THC63LVD1025

Benefits

  • support full HDTV @120hz (3DTV)
  • Lowest bounding pad count
  • Low cost IP
  • reliability
  • highly adjustable
  • customization for your own design

What’s Included?

  • Design kit includes :
  • - LEF view and abstract gdsII
  • - Verilog HDL behavioral model
  • - Liberty (.lib) timing constraints for typical, worse and best corner case
  • - Full Datasheet /Application Note with integration guidelines document
  • - Silicon characterization report when available
  • Tapeout kit includes the design kit plus plysical view:
  • - gdsII
  • - LVS netlist and report
  • - DRC/ERC/ESD/ANT report

Specifications

Identity

Part Number
VT40LVD1025
Vendor
V-Trans Microelectronics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact V-Trans Microelectronics

Learn more about V-By-One IP core

The Benefits of a Multi-Protocol PMA

At Silicon Creations, we have developed a power and area optimized, flexible and programmable PMA (Physical Medium Attachment) architecture that can be reliably ported to different process nodes and scaled across protocol generations as data rates increase. It is called the Multi-Protocol PMA, or MP-PMA for short.

Frequently asked questions about V-by-One IP cores

What is Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression?

Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression is a V-By-One IP core from V-Trans Microelectronics listed on Semi IP Hub.

How should engineers evaluate this V-By-One?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this V-By-One IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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