Overview
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI Express endpoints. The IP connects seamlessly to Altera PCI Express Hard IP cores, providing a transparent high-speed data path over PCI Express.
The Lancero Design Kit offers a complete end-to-end hardware IP core and software driver solution for exchanging full-duplex, high bandwidth streaming data over PCI Express with your embedded processor. The simple, easy to use Altera SOPC interface of the Lancero provides developers with the ability to easily integrate their custom FPGA logic with PCI Express and Linux/Windows applications without worrying about having detailed working knowledge of PCIe.
It is available in two basic configurations; Lancero Target Bridge and Lancero Descriptor Bridge with a SGDMA IP Core. The Target Bridge configuration is ideal for small PCI express endpoints, which just require simple register access. The Descriptor Bridge SGDMA configuration provides for very high-speed DMA transfers with minimal CPU overhead.
Device Drivers
The Lancero device drivers use the operating system standard interface, either Linux IEEE POSIX or the Windows programming interface. The drivers provide one character device interface for the control bus, one character device interface for SGDMA and one character device interface for user interrupts.
A major benefit of the Lancero SGDMA solution is its ability to perform large SGDMA transfers directly to and from the users application buffers, without the need for in-kernel copies associated with regular DMA controllers.
By providing a control bus and data bus with SGDMA engines, developers can now process high performance data transfers between the FPGA logic and your Linux application making this an ideal solution for:
Hardware designers using the Avalon MM and ST bus interfaces from Altera
Software designers: only require Linux read/write() or Windows Read/WriteFile() functions
Learn more about PCI Express IP core
Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).
Geeta Arora, Cadence
Madhumita Sanyal, Synopsys