Ethernet Real-Time Publish-Subscribe (RTPS) IP Core

The Real-Time Publish-Subscribe (RTPS) core provides a complete hardware IP solution for the Ethernet RTPS protocol.

The core provides OMG DDSI-RTPS compliance, hardware-based message label filtering, hardware mapping of message label to host memory, and complete offload of RTPS handling including: Transmit messages, Receive messages, IEEE 1588 Precision Time Protocol (PTP), DMA controller, frame building/checking, and CRC generation/ checking.

The host interface to the core is AXI4. This allows the core to be connected to an external host processor over PCIe or to an embedded SoC processor. The core is built for dropping into an FPGA and providing the complete design from processor interface to Ethernet RTPS network interface.

This core is targeted towards applications in military/aerospace and has been implemented on AMD (Xilinx) UltraScale™/UltraScale+™ devices. The core comes with test benches, constraints and an example design, making design integration a straightforward task.

The vendor has a set of standard form factor boards featuring FPGAs, 10G Ethernet optics, and off-the-shelf reference designs for quick evaluation of the IP core.
 

• OMG DDSI-RTPS 2.2 compliant interface with hardware-based offload
• Hardware DMA engines with message label mapped buffers
• Message label validation and filtering
• Host processor offloaded from all networking responsibilities
• Supports 10G data rate
• Configurable number of ports in a single FPGA
• AXI4 host interface for embedded or PCIe-based processors
• Frame counter and error statistics

• Increased performance with hardware-based Ethernet RTPS offload
• Hardware-based message label filtering and host DMA setup
• Leverage proven technology for standard interface implementation
• Mitigate obsolescence

• Avionics vehicle and mission systems
• Industrial/Machine vision systems