ChipScope Pro IBERT for 7 Series GTZ
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is d…
- Test / Debug
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
ChipScope Pro IBERT for 7 Series GTZ
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTZ transceivers is d…
ChipScope Pro IBERT for 7 Series GTP
The customizable LogiCORE™ IP ChipScope™ Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTP transceivers is d…
AXI4-Stream Accelerator Adapter
The AXI4-Stream Accelerator Adapter is a soft Xilinx® LogiCORE™ Intellectual Property (IP) core used as a infrastructure block fo…
AXI Memory Mapped to PCI Express (PCIe) Gen2
The AXI Memory Mapped to PCIe® Gen2 IP core provides an interface between the AXI4 interface and the Gen2 PCI Express (PCIe) sili…
AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
7 Series Gen2 Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
AXI 1G/2.5G Ethernet Subsystem
The AXI Ethernet Subsystem provides a control interface to internal registers via a 32-bit AXI4-Lite Interface subset.
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
MIPI CSI-2 RX Controller Subsystem
The Xilinx MIPI CSI2 Receiver Subsystem implements the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (…
The Xilinx® CAN IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control un…
The Xilinx® LogiCORE™ IP 10G/25G Ethernet solution provides a 10 Gigabit or 25 Gigabit per second (Gbps) Ethernet Media Access Co…
MIPI SoundWire is low-complex, low-power, low-latency interface that supports multi-channel data.
Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices.
The SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs.
MPEG Transport Stream Multiplexing & Encapsulation Engine
The MTS-E core multiplexes and encapsulates audio, video, and metadata streams in a single MPEG Transport Stream (MTS), and optio…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
This UHS2PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed i…
Xilinx 40G/100G Ethernet LogiCORE based on Sarance Technologies Best-In-Class Intellectual Property Xilinx High-Speed Ethernet Lo…
HDLC & SDLC Protocol Controller
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC…
MPEG-2 Transport Stream Encapsulation for SMPTE2022
The IPX-MPEG2-TS IP-cores are designed to be used with intoPIX video codecs.