USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
- UCIe 1.1
- UMC
- 55nm
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Enhancement) Logic Process, without internal power clamping circuit
UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
UMC 28nm HPC/Low-K process , 1.25G-16Gbps 4-Lane SERDES
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
3.3V LVDS Transmitter 16~100MHz; 55nm SP/RVT LowK Logic Process
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process
UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process
10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%.
Display Stream Compression (DSC 1.2) Encoder
The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K.
10/100/1000 Tri-MAC 8-bit core with MII/GMII/RGMII interface @ 125MHz/25MHz/2.5MHz Solution
The 10/100/1000Mbps Tri-mode Ethernet MAC offers an IEEE802.3-2015 compliant solution that meets the requirements for tri-mode LA…
The GiGE/Triple-speed Ethernet MAC offers an IEEE802.3-2015 compliant solution that meets the requirements for GiGE/tri-mode LAN …
10G Low latency, 32-bit MAC + PCS @ 312.5MHz Solution (32-bit and 64-bit UI)
The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2015 compliant package for NIC (Network Interface Card…
10G Ultra Low latency, 32-bit MAC + PCS Solution (32-bit and 64-bit UI)
The 10Gbps 32-bit Ethernet IP solution offers a fully integrated IEEE802.3-2015 compliant package for NIC (Network Interface Card…