CAN with Flexible Data Rate (CAN FD)
The Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…
- CAN / CAN-FD / CAN-XL
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
CAN with Flexible Data Rate (CAN FD)
The Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…
The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible prod…
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters.
7 Series Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
The Xilinx® LogiCORE™ IP 40G/50G Ethernet solution provides a 40 Gigabit or 50 Gigabit per second (Gbps) Ethernet Media Access Co…
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
GLOBALFOUNDRIES 28nm SLP sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
GLOBALFOUNDRIES 65nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The Bitec HDMI 2.0b IP Core enables HDMI interconnectivity without the need for external HDMI ASSP devices.
DisplayPort heralds a new alternative in video connectivity.
40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process
USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process