The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described…
- Single-Protocol PHY
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Lattice 2.5 Gbps Ethernet PCS IP core implements the state machine functions for the physical coding sublayer (PCS) described…
The 2.5GMAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
The GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA ORT42G5 FPSC and provides the PCS …
The 10 Gigabit Ethernet Extended Sublayer (XGXS) Intellectual Property (IP) Core enables the creation of system solutions for 10 …
The 10 Gigabit Ethernet (10 GbE) Physical Coding Sublayer (PCS) solution from Lattice Semiconductor enables creation of system so…
UltraScale+ Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS),…
UltraScale+ Device Integrated Block for PCI Express (PCIe)
The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…
UltraScale Integrated 100G Ethernet Subsystem
Xilinx offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC) and Physical Coding Sublayer (PC…
UltraScale / UltraScale+ Interlaken
The Xilinx® LogiCORE™ IP UltraScale™ architecture integrated IP core for Interlaken is a scalable chip-to-chip interconnect proto…
MIPI DSI TX Controller Subsystem
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…
MIPI CSI Controller Subsystems
The Xilinx MIPI CSI2 Receiver Subsystem and MIPI CSI 2 Transmitter Subsystems implement the Mobile Industry Processor Interface (…
The LogiCORE In-System IBERT IP enables 2D eye scans of Ultrascale™/Ultrascale+™ transceivers to be performed the in Vivado® Seri…
Hard-core Tri-mode Ethernet MAC
The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…
ChipScope Pro (IBERT) for Virtex-6 GTH
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
CAN with Flexible Data Rate (CAN FD)
The Xilinx® CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control…
The LogiCORE™ IP AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of ARM® AMBA® AXI control interface compatible prod…
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters.