Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: Single-Protocol PHY

SMIC 55nm sub-LVDS Receiver

The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.

SMIC 55nm LL Pre-Silicon View all specifications

Overview

The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only.

Key features

  • Supports Aptina HiSPi, Panasonic LVDS, or Sony LVDS parallel input signal
  • 10 data channels / 2 clock channel integrated
  • Maximum serial data rate per channel: 1Gbps
  • Supports up to 20-bit CMOS parallel input (DVP input mode)
  • Each channel configurable independently
  • Controllable 100? on-chip termination resistor
  • De-serializes the serial inputs with a configurable ratio (8 / 10 / 12 / 14 / 16)

Silicon Options

Foundry Node Process Maturity
SMIC 55nm LL Pre-Silicon

Specifications

Identity

Part Number
S55LLV33_SUBLVDSRX_03
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is SMIC 55nm sub-LVDS Receiver?

SMIC 55nm sub-LVDS Receiver is a Single-Protocol PHY IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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