Vendor: Macnica Category: SLVS-EC

SLVS-EC Receiver IP

Next generation CMOS image sensor interface SLVS-EC is the next-generation, high-speed interface for high-resolution CMOS image s…

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Overview

Next generation CMOS image sensor interface

SLVS-EC is the next-generation, high-speed interface for high-resolution CMOS image sensors.

This standard is tolerant of lane-to-lane skew because of embedded clock technology that simplifies board-level design of high-speed and long-distance data transmission.

Originally developed and licensed by Sony, SLVS-EC is now starting to be supported by multiple image sensor suppliers.

Specifications

Feature Description
Number of Lanes 1, 2, 4, 6, 8
Baud Grade

1 (1.152 to 1.25 Gbps)

2 (2.304 to 2.5 Gbps)

3 (4.608 to 5.0 Gbps - supported in v2.0)
Bit per Pixel 8, 10, 12, 14, 16
CRC Limited*
ECC Supported
Embedded Data Supported
Dynamic Mode Change Supported
Multiple Stream If needed

Supported Devices

  • Intel Cyclone V GX/SX (v1.2)
  • Intel Cyclone 10 GX (v1.2 / 2.0)
  • Intel Arria 10 GX/SX (v1.2 / 2.0)
  • Xilinx Artix 7 (v1.2)
  • Xilinx Kintex 7 (v1.2 / 2.0)
  • Xilinx Kintex Ultrascale (v1.2 /2.0)
  • Xilinx Kintex Ultrascale (v1.2 / 2.0)

evice Resource Utilization

Resource Utilization in case of 8 LANE Full Configuration

Items Cyclone® V GX Arria® 10 GX
  w/o ECC w/ECC w/o ECC w/ECC
ALMs 4711 8242 3930 7555
Total Registers 4328 6664 3778 6079
Total block memory bits 4096 13312 2560 11776

Key features

  • Compliant with SLVS-EC Specification v1.2 and v2.0 by Sony
  • Supports various functions defined by the SLVS-EC Link layer (FPGA dPCS/PMA is used as Physical layer)
  • Supports Byte-to-Pixel conversion for various lane-configurations
  • Supports Header analysis and Payload error detection

Block Diagram

SLVS-EC Rx IP block diagram

What’s Included?

  • Encrypted RTL (Verilog HDL)
  • Reference design
  • Simulation environment (For ModelSim)
  • User's manual, Reference manual

Specifications

Identity

Part Number
SLVS-EC Rx IP
Vendor
Macnica
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Macnica
HQ: USA
Contact Macnica

Learn more about SLVS-EC IP core

The Benefits of a Multi-Protocol PMA

At Silicon Creations, we have developed a power and area optimized, flexible and programmable PMA (Physical Medium Attachment) architecture that can be reliably ported to different process nodes and scaled across protocol generations as data rates increase. It is called the Multi-Protocol PMA, or MP-PMA for short.

How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications

FPGAs are at home in the world of multi-gigabit-per-second signal conversion and bridging. In high-bandwidth telecoms, network and data center equipment, the FPGA is a mainstay of system designs, offering a valuable combination of high-speed SerDes capability, extensive logic resources, and programmability, giving designers the flexibility to modify features and functions without changing their board layout.

Frequently asked questions about SLVS-EC IP cores

What is SLVS-EC Receiver IP?

SLVS-EC Receiver IP is a SLVS-EC IP core from Macnica listed on Semi IP Hub.

How should engineers evaluate this SLVS-EC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SLVS-EC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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