Vendor: Arteris Category: Network-On-Chip

Ncore Cache Coherent Interconnect IP

High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.

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Overview

High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.

Built on more than a decade of volume silicon, Ncore™ is silicon-proven coherent NoC IP that is highly configurable, power-efficient, and works with any processor, including Arm® and RISC-V.

  • Extends full cache-coherency across chiplets for rapid, modular innovation.
  • ISO 26262 ASIL D ready.
  • Pairs with Magillem® automation for IP integration software, so teams can scale modular architectures, simplify multi-die design and compress development schedules.

Combining Ncore and FlexNoC gives designers foundational technology for unparalleled performance optimization, scalability, and system integration in an expanded multi-die solution. This enables robust cache-coherence, efficient communication, and flexibility, which can result in market differentiation and accelerated time-to-market.

 

Key features

  • Highly scalable system
  • True heterogeneous coherency with mixed AMBA CHI and AMBA ACE support
  • Full coherency for cached processors and I/O coherency for accelerators
  • Multi-die cache coherency over UCIe™ 1.1 via an AMBA CXS.B interface — up to four chiplets, and up to 4 × 128 GB/s links per die*
  • Configurable network and topologies
  • Mesh topology with physical tiling of repetitive blocks*
  • Functional safety with FMEDA generation and ASIL D certification*
  • Configurable snoop filters
  • I/O proxy cache and system memory cache
  • Low power consumption
  • Quality of service (QoS)
  • Debug and trace/monitoring

Block Diagram

Ncore 3 block diagram

Benefits

Higher frequencies, lower latencies

Use of multiple configurable snoop filters to accommodate different cache organization.

Lower power consumption

Fewer off-chip main memory accesses result in lower power consumption.

Smaller die area

Fewer wires use the optimal NoC transport layer.

Easy configuration

Ncore adapts to each coherent agent’s behavior and characteristics.

Faster time to market

Tiling accelerates physical design, implementation, and timing closure.

Flexible topologies

Choose from crossbar, mesh, and ad-hoc topologies.

Safety

Automated FMEDA safety documentation and ISO26262 ASIL B to D certified.

Automated verification

Save hundreds of hours of work compared to manual verification generation.

Shorter schedules

Fewer iteration loops speed development time.

Specifications

Identity

Part Number
Ncore Cache Coherent Interconnect IP
Vendor
Arteris
Type
Silicon IP

Videos

Ncore Cache Coherent Network-on-Chip IP from Arteris
Introducing the latest release of Ncore from Arteris, the only scalable, highly configurable, cache coherent NoC that is ISO 26262 certified for modern SoC designs. Learn how engineering teams can derisk their SoC designs and deliver on their vision in record time, saving upwards of 50 years of engineering effort per project compared to manually generated interconnect solutions.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Arteris
HQ: United States
Contact Arteris

Learn more about Network-On-Chip IP core

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Accelerating RISC-V development with network-on-chip IP

In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem. Choices range from single processor cores to clusters to multiple core clusters that are predominantly heterogeneous but occasionally homogeneous.

Network-on-chip (NoC) interconnect topologies explained

Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Meet the Next-Generation Network-on-Chip From Arteris

Today’s system-on-chip (SoC) designs continue to grow in capacity and complexity. The only way to continue developing components of this class is by increasing the sophistication of the design, implementation and verification tools while simultaneously increasing levels of automation. The launch of the latest generation of network-on-chip (NoC) IP, FlexNoC 5, from Arteris addresses all these issues.

Why network-on-chip IP in SoC must be physically aware

Today, multicore system-on-chip (SoC) designs can be composed of hundreds of IP blocks, typically containing up to ten million logic gates. One way for SoC developers to create devices of this complexity is to make use of proven IP blocks provided by trusted third-party vendors.

Frequently asked questions about NoC IP cores

What is Ncore Cache Coherent Interconnect IP?

Ncore Cache Coherent Interconnect IP is a Network-On-Chip IP core from Arteris listed on Semi IP Hub.

How should engineers evaluate this Network-On-Chip?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Network-On-Chip IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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