USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
- TSMC
- 22nm
- ULL
High-Speed Serial IP cores enable the high-bandwidth connectivity required by modern SoCs, AI accelerators, networking equipment, storage systems, telecom infrastructure, aerospace platforms, and data center devices. These IP solutions provide reliable, standards-compliant communication between chips, boards, systems, and external networks.
This catalog includes IP cores supporting industry-standard protocols such as PCI Express, CXL, Ethernet, USB, Fibre Channel, SAS, InfiniBand, Interlaken, JESD204, Optical Transport, CPRI, RapidIO, UniPro, CoaXPress, SpaceWire, and other high-speed serial interfaces. Solutions may include PHYs, controllers, protocol stacks, subsystem IP, and verification components.
Compare high-speed serial IP offerings from multiple vendors based on supported standards, data rates, feature sets, protocol compliance, silicon efficiency, and target applications to identify the right connectivity solution for advanced ASIC and SoC designs.
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
USB 2.0 OTG Controller - SMIC 55nm Eflash
IP
CoaXPress Multi-Device Multi-Stream Host
The CoaXPress standard defines a cost effective and easy interfacing between video devices and acquisition hardware over RG59 and…
CoaXPress Multi-Link Multi-Stream Device
The CoaXPress standard defines a cost effective and easy interfacing between video devices and acquisition hardware over RG59 and…
High Channel Count DMA IP Core for PCI-Express
The High Channel Count (HCC) DMA IP core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.
Next generation CMOS image sensor interface SLVS-EC is the next-generation, high-speed interface for high-resolution CMOS image s…
Silicon agnostic Ethernet MAC IP for lower speeds from 10M to 2.5G Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables th…
Ultra compact Ethernet Switch designed for easy use, targets applications requiring low size and a versatile solution The 1G Ethe…
Silicon agnostic Ethernet TSN MAC IP with speeds of 10G and 25G, based IEEE 802.3 Ethernet Layer 2 solution with support for key …
10G Ultra Low Latency Ethernet Solution
The 10Gbps Ultra Low Latency Ethernet IP solution offers a fully integrated IEEE802.3 compliant package for NIC (Network Interfac…
USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with…
Atomic Rules UDP Offload Engine (UOE) is a UDP FPGA IP Core that allows for immediate operation at 10, 25, 40, 50, 100 or 400 GbE.
The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification.
iWave provides the user application for PCI-e target bridge to access the control & status registers of custom logic and data tra…
1G Deep Buffering Memory Ethernet Switch IP Core
switch supporting buffering of large amounts of data in external DDR RAM The 1G deep buffering memory Ethernet Switch is an Ether…
LTTS USB 2.0 OTG controller are designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s and USB O…
The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applicati…
UDP/IP – 100 GbE Protocol Hardware Stack
The DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100…
Fully compliant with the VSF (Video Services Forum) Technical Recommendation, "Transport of JPEG 2000 Broadcast profile video in …
Multi-Channel Flex DMA IP Core for PCI Express
The Multi-Channel DMA IP Core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.