What is USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core?
USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core is a USB IP core from T2M GmbH listed on Semi IP Hub.
Vendor:
T2M GmbH
Category:
USB
USB 3.0 OTG High / Full / Low- Speed Dual Role IP Core
USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with…
Overview
USB 3.0 OTG Controller IP is based on the latest USB 3.0 specification from USB Implementer Forum (USBIF) and is compatible with the latest xHCI 1.1 specification. It supports SuperSpeed (5Gbps) link speed, backward compatible with HighSpeed (480Mbps), FullSpeed (12Mbps) and LowSpeed
(1.5Mbps). USB 3.0 Controller IPs are based on a nextgeneration unified architecture which is designed directly for USB 3.0 specification and optimized intensively for logic sharing.
(1.5Mbps). USB 3.0 Controller IPs are based on a nextgeneration unified architecture which is designed directly for USB 3.0 specification and optimized intensively for logic sharing.
Key features
- Support SW controlled host/device role switching.
- Support Superspeed, Highspeed and Fullspeed
- Support Control, Bulk, Interrupt and Isochronous Transfer Types
- Support U1/U2/U3 power saving modes for USB 3.x port
- Support L1/L2 power saving modes for USB 2.0 port
- Support Hardware LMP Capability and BESL LMP Capability for USB 2.0 ports in host mode
- Support MSI/MSI-X Interrupts and Legacy Interrupt
- Fully Support for Isochronous Transfer error handling, support error conditions like Isochronous Buffer Overrun, Bandwidth Overrun, Missed Service Error, Ring Overrun/Underrun, Parameter Error, etc. in host mode
- Fully Support for Event Data TRB, multiple Event TRBs can be used in one TD in host mode
- Fully Support for Hardware Bandwidth Management, support error conditions like Resource Error, Bandwidth Error and Secondary
- Bandwidth Error in host mode
- xHCI-like ring management, TRB definitions and doorbell mechanism in device mode
- Low-MIPS Operational Model.
- Pipelined transfer mechanism to achieve continuous data streaming
- Fully Support for Scatter-and-Gather, all TRBs can points to byte-aligned buffers without alignment limitation
- Innovative Active TRB Prefetching technology to eliminate TRB access latency and improve system performance
- Dynamically reconfigurable Endpoint type, software can reconfigure the same Physical Endpoint to operate as Bulk, Interrupt or Isochronous EP
- Dynamic data buffer allocation for all endpoints, Tx/Rx Data Buffers can be shared by endpoints to optimize RAM usage
- Configurable number of supported device slots (up to 64) in host mode
- Configurable number of supported active Endpoints (up to 128) in host mode and Device mode
- Configurable numbers of USB 3.x ports and USB 2.0 ports respectively in host mode
- Configurable system bus type (AXI4/AXI3/AHB/APB) and width
- Configurable USB 3.x/2.0 PHY type (PIPE/UTMI+/ULPI) and width.
Block Diagram
USB 3.0 OTG Controller IP block diagram
What’s Included?
- The USB 3.0 OTG Controller interface is available in Source and netlist products.
- The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Specifications
Identity
Part Number
USB 3.0 OTG Controller IP
Vendor
T2M GmbH
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Frequently asked questions about USB IP cores
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.