Vendor: Atria Logic, Inc. Category: Ethernet

10/100/1000 Mbps Ethernet MAC

The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification.

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Overview

The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification. This core transmits and receives Ethernet frames to and from Ethernet network in all three speeds 10/100/1000 Mbps. Both half-duplex and fullduplex mode of operation are supported at all three speeds. The core interfaces to an industry standard external PHY device through RGMII or GMII for Gigabit Ethernet and RGMII or MII for fast Ethernet.

This core is implemented in both Altera Cyclone-III and Xilinx Virtex-4 FPGA. This core also supports pause frame control based on user programmable register setting.

The core has the following modules:

Transmitter
Receiver
MDIO (Management Data Input Output interface)
RGMII,GMII and MII interface
Optional Read and Write DMA Engine
Configuration and Status Registers for Tx, Rx and MDIO
PHY Logic for Ethernet I/O

Key features

  • Designed according to IEEE 802.3-2005 Specification.
  • Support 10/100/1000 Mbps Ethernet MAC Speed in Halfduplex and Full-duplex mode.
  • Promiscuous receive mode support.
  • Untagged frames support.
  • Support for Reduced Gigabit Media Independent Interface (RGMII) in all three speeds 10/100/1000 Mbps.
  • Support for Gigabit Media Independent Interface (GMII), Media Independent Interface (MII).
  • Support for Management Data Input Output (MDIO) interface to access configuration and status registers in PHY device.
  • Supports for Pause Frame control from internal receive buffer and external CPU.
  • Optional Programmable IFG value.
  • CRC generation and checking both on transmit side and receive side.
  • Option for user FCS field passing.
  • Automatic padding on transmit side and option for remove padding on receive side.
  • Support for read and write DMA engines for DDR memory.

Block Diagram

AL_EMAC_CORE block diagram

What’s Included?

  • HDL RTL source code or EDIF netlist for FPGA
  • Self-checking Testbench in Verilog.
  • Simulation scripts, vectors, expected results, and comparison utility
  • Synthesis and STA scripts.
  • Comprehensive user documentation, including detailed specifications and a system integration guide

Specifications

Identity

Part Number
AL_EMAC_CORE
Vendor
Atria Logic, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Atria Logic, Inc.

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Frequently asked questions about Ethernet IP cores

What is 10/100/1000 Mbps Ethernet MAC?

10/100/1000 Mbps Ethernet MAC is a Ethernet IP core from Atria Logic, Inc. listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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