Vendor:
M31 Technology Corp.
Category:
USB
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
Overview
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Clock) function that eliminates the need for an external crystal oscillator. During USB data transfer, the IP performs a background calibration to ensure frequency accuracy. The USB IP with BCK complies with the USB-IF specification and has the same electrical performance as the standard USB IP.
Key features
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
- Data UI (unit interval) is well-controlled within ±500ppm during data transfer
- Concise and explicit design structure to ease the IP integration
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 22nm | ULL | — |
Specifications
Identity
Part Number
M31 BCK Technology Specialized for Peripheral Applications
Vendor
M31 Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
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Frequently asked questions about USB IP cores
What is USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)?
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm) is a USB IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.