iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.
- PCI Express
- Not Applicable
- Available
- FPGA IP Core
High-Speed Serial IP cores enable the high-bandwidth connectivity required by modern SoCs, AI accelerators, networking equipment, storage systems, telecom infrastructure, aerospace platforms, and data center devices. These IP solutions provide reliable, standards-compliant communication between chips, boards, systems, and external networks.
This catalog includes IP cores supporting industry-standard protocols such as PCI Express, CXL, Ethernet, USB, Fibre Channel, SAS, InfiniBand, Interlaken, JESD204, Optical Transport, CPRI, RapidIO, UniPro, CoaXPress, SpaceWire, and other high-speed serial interfaces. Solutions may include PHYs, controllers, protocol stacks, subsystem IP, and verification components.
Compare high-speed serial IP offerings from multiple vendors based on supported standards, data rates, feature sets, protocol compliance, silicon efficiency, and target applications to identify the right connectivity solution for advanced ASIC and SoC designs.
iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.
PCIe to ISA bride is a IP core which converts PCIe to ISA master bus interface.
PCI Controller provides an interface between the PCI bus and user interface.
Common Public Radio Interface (CPRI) v.6.1 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
Fast, reliable connectivity in any FPGA using a minimum of FPGA resources The TCP/IP (Transmission Control Protocol/ Internet Pro…
The Microtronix Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfa…
The MVD RTP Receiver allows the reception and the processing of an RTP stream.
The MVD Multi-RTP transmitter allows the transmission of several RTP streams on an Ethernet Network.
This RTP Transmitter IP core implements a full Hardware RTP Transmitter.
High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3 Clause 5 and 4 respectively) Edition 4.0 protocols
Interlaken is a royalty-free interconnect protocol that was developed by Cisco Systems and Cortina Systems in 2006.
DO-254 Tri-Mode Ethernet Media Access Controller (TEMAC) 1.00a
Consists of a separate transceiver (transmitter) and receiver IP core implementing a point to multipoint communication channel bu…
DO-254 ARINC 818 XGA Transceiver
Provides an easy way to implement ARINC 818 compliant interfaces in Xilinx® FPGAs.
GDA's USB 3.0 SSIC controller is a configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with th…
The 10/100/1000Mbps Tri-mode Ethernet MAC offers an IEEE802.3-2008 compliant solution that meets the requirements for tri-mode LA…
Certified USB 5G & 10G Dual Mode Controller
USB 5G, 10G Dual Mode controller is a configurable core and implements the USB Host functionality or USB Device functionality sel…
10/100 Mb Media Access Controller with RMII
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite int…
100G Ethernet Solution (MAC + 100GBase-R PCS)
The 100Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Eth…
Common Public Radio Interface (CPRI) v.5.0 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…