The Display controller (DISP) provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchroniza…
- Display Controller
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
The Display controller (DISP) provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchroniza…
The Graphic 2D Accelerator (G2D) is a specialized DMA dedicated to image manipulation.
The H.265 (HEVC – High Efficiency Video Coding) Decoder IP core delivers high-performance video decompression for next-generation…
The H.265 (HEVC – High Efficiency Video Coding) Encoder IP core enables efficient, high-quality video compression for application…
The H.264 Decoder IP Core offers a high-efficiency video decoding solution tailored for a wide range of applications, including m…
The H.264 Encoder IP Core delivers a high-performance video compression solution ideal for applications such as surveillance, bro…
Designed for AI-driven video pre-processing, ensuring quality optimization with low latency and real-time performance
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Warp Intel® FPGA IP provides a optimized solution fo…
Video and Vision Processing Suite
The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) funct…
Tone Mapping Operator (TMO) Intel® FPGA IP
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the Tone Mapping Operator (TMO) Intel® FPGA IP corrects …
The Lancero JPEG-LS Lossless Image Encoder for FPGAs is an efficient implementation of the best-in-class lossless image compressi…
H.265 - Efficient video compression for high-quality, low-bandwidth streaming
H.265 (HEVC) is a video compression standard that offers up to 50% better compression efficiency than H.264, reducing bandwidth u…
H.264 - Efficient video compression for high-quality streaming and playback
H.264 (also known as AVC) is a video compression standard that ensures high-quality video delivery with minimal bandwidth usage.
H.265 Codec - Efficiently compresses high-quality video for streaming and storage
H.265 (HEVC) is a cutting-edge video compression standard that delivers superior video quality at lower bit rates compared to H.2…
H.264 Codec - Efficient video compression for high-quality streaming and playback
H.264, also known as AVC, is a high-performance video compression standard that offers superior quality at lower bit rates.
Arm Immortalis-G925 is Arm’s latest flagship GPU, based on 5th Gen Arm GPU architecture, designed to provide the best gaming and …
Cost-efficiency, AI-based noise reduction IP
The AI-NR series IPs offer noise reduction solutions for optimizing image quality in low-light or complex lighting conditions.
High-efficiency, AI-based super resolution IP
The AI-SR series IPs offer super resolution solutions for enhancing video quality and pixel resolution, primarily used for post-p…
This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 s…
JPEG XS Decoder (FPGA) - Performance-oriented version
TMC’s JPEG XS IP maximizes the advantages of FPGAs and helps customers improve the competitiveness of their products.