JPEG 2000 120P Encoder/JPEG 2000 Decoder
The JPEG 2000 Broadcast family has been designed to respond to the various applications of the Broadcast markets.
- JPEG 2000
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
JPEG 2000 120P Encoder/JPEG 2000 Decoder
The JPEG 2000 Broadcast family has been designed to respond to the various applications of the Broadcast markets.
"DCI" 2K JPEG 2000 Encoder/JPEG 2000 Decoder
D-Cinema and the Beyond Cinema JPEG 2000 families have been especially designed to meet today’s requirement of the Digital Cinema…
Beyond VGA Display Controller core provides VGA capabilities for embedded systems.
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
Bit Block Transfer 2D video accelerator
The logiBITBLT is 2D graphic accelerator or BitBlitter IP core from Xylon logicBRICKS™ IP library.
Compact Multilayer Video Controller
The logiCVC-ML IP core is an display graphics controller that enables an easy video and graphics integration into embedded system…
HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
Graphics, compute and AI all on one processor, with one software stack
AMBA 5 AHB Bus TFT LCD / OLED Display Controller
The Digital Blocks DB9000AHB5 Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 5 AHB b…
AMBA AXI5 / ACE5-Lite TFT LCD / OLED Display Controller
The Display Controller IP Core interfaces a microprocessor and frame buffer memory via an AMBA AXI5 / ACE5-Lite Protocol Interconnect to a TFT LCD or OLED display panel.
Real-time Pixel Processor for Vision applications
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable Standard Dynamic Range (SDR) capabl…
VID_OVERLAY is a versatile video multiplexer that allows one video stream to be inserted over another.
Digital Video Anti-aliasing filter IP Core
The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications.
High-Perfomance, multi-format Video Encoder IP
The E300 Series of Encoder IP features a new hardware architecture that minimizes the silicon area while enabling 4K resolution e…
As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an ef…
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
Image Codec/Encoder/Decoder - ISO/IEC 10918-1 JPEG standard
The CMS-1 is a parameterized integration of the VSC-1 scaler core with other IP as needed for ABR and similar applications requir…
Video CODEC - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
High performance with better image quality
Video Decoder - AV1, HEVC, AVC, VP9
High performance with better image quality
Video Decoder - AV1, HEVC, AVC
High performance with competitive size