Vendor:
Beyond Semiconductor
Category:
Display Controller
VGA/LCD Display Controller
Beyond VGA Display Controller core provides VGA capabilities for embedded systems.
Overview
Beyond VGA Display Controller core provides VGA capabilities for embedded systems. It supports both CRT and LCD displays with user programmable resolutions and video timings, thus providing compatibility with almost all available LCD and CRT displays.
The core supports a number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp grayscale, and 8bpp-pseudo color. The video memory is located outside the primary core, thus providing the most flexible memory solution possible. It can be located on-chip or off-chip, shared with the system’s main memory (VGA on demand) or be dedicated to the VGA system. Image data is fetched automatically via the WISHBONE Master interface, making this an ideal “program-and-forget” video solution. More demanding video applications, like streaming video or video games, can benefit from the video-bank-switching function. Flicker and cluttered images are reduced by automatically switching between video-memory pages and/or color lookup tables on each vertical retrace.
The horizontal, vertical, and composite synchronization polarization levels, as well as the blanking polarization level are programmable by software.
The core supports a number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp grayscale, and 8bpp-pseudo color. The video memory is located outside the primary core, thus providing the most flexible memory solution possible. It can be located on-chip or off-chip, shared with the system’s main memory (VGA on demand) or be dedicated to the VGA system. Image data is fetched automatically via the WISHBONE Master interface, making this an ideal “program-and-forget” video solution. More demanding video applications, like streaming video or video games, can benefit from the video-bank-switching function. Flicker and cluttered images are reduced by automatically switching between video-memory pages and/or color lookup tables on each vertical retrace.
The horizontal, vertical, and composite synchronization polarization levels, as well as the blanking polarization level are programmable by software.
Key features
- Resolutions of up to 2048x2048 @ 60Hz in ASIC. Higher resolutions are possible, depending on silicon process
- Resolutions of up to 1024x1024 @ 60Hz in FPGA. Higher resolutions are possible, depending on FPGA speed grade
- 32 bits per pixel (bpp), 24bpp and 16bpp color modes
- 8bpp grayscale and 8bpp pseudo-color modes
- Horizontal and verical image scaling by integer factors
- CRT and LCD display support
- Separate VSYNC/HSYNC and composite CSYNC synchronization signals
- Composite BLANK signal
- User programmable video timing
- User programmable video resolutions
- User programmable video control signals polariy
- Supports video bank switching during vertical retrace
- AHB or 32bit WISHBONE RevB.3 compliant Slave and Master interfaces
- Operation from a wide range of input clock frequencies
- Static, synchronous design
- Fully synthesizable
Applications
- Embedded GUI
- Embedded multimedia
- Multi-function printer display
- Portable media player
- Video camcorder
- Digital camera
- GPS and navigation instruments
What’s Included?
- Soft core RTL in Verilog
- Test bench in Verilog
- Programming interface document
- Engineering support
- An evaluation platform is available for purchase separately
Specifications
Identity
Part Number
VGA/LCD Display Controller
Vendor
Beyond Semiconductor
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Slovenia
Learn more about Display Controller IP core
Empowering AI-Enabled Systems with MIPI C/D-PHY Combo IP: The Complete Audio-Visual Subsystem and AI
High Speed, Low Power and Flexibility Drive DisplayPort's Increasing Popularity
In this article we provide an introduction to DP, talk about the various factors that IC designers will want to consider when integrating the DP functionality into their SOC, and present at a high-level the solutions Silicon Creations provides in this area.
The whys and hows of secure boot
With the proliferation of Internet of Things (IoT) devices, which now span just about every walk of life, from smart cities to wireless jewellery, the need to prioritize security in IoT-style embedded systems has never been greater. The secure boot process is a vital first step in securing any embedded system, a necessary part of your application’s anti-malware fortress. Let’s take a look at the pros and cons, with a focus on one of the most popular processors in electronics – the i.MX6.
Motion Picture: a Reality on Emulation Platform
In present day’s situation, whenever we are in the phase of designing a cluster SoC, we have no reliable way of verifying our design in real case scenarios, or showcase the possibilities of our design through any demos. This, sometimes, paves way for critical design bugs which requires re-spins/cuts.
Sequential clock gating maximizes power savings at IP level
In this paper we talk about design exploration using the PowerPro tool. For analysis of power optimization based on this tool, we have included Advanced Driver Assistance System (ADAS) and cluster IPs with high speed processing requirements. These IPs have multiple complex operation requirements within a clock period, making them ideal candidates for power saving. The IPs under consideration are image processors, high-speed bus fabrics for a memory controller, display controllers, and video codecs.
Frequently asked questions about Display Controller IP
What is VGA/LCD Display Controller?
VGA/LCD Display Controller is a Display Controller IP core from Beyond Semiconductor listed on Semi IP Hub.
How should engineers evaluate this Display Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Display Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.