Video CODEC - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
High performance with competitive size
- AV1 + 2
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
Video CODEC - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
High performance with competitive size
The DB1810 Color Space Converter IP Core transforms three color components from one color space to another.
BitBLT Graphics Hardware Accelerator (Avalon Bus)
The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comma…
2D Graphics Hardware Accelerator (AHB Bus)
The Digital Blocks DB9200AHB 2D Graphics Hardware Accelerator Verilog IP Core renders graphics frames as follows: Generates bitma…
2D Graphics Hardware Accelerator (AXI Bus)
The Digital Blocks DB9200AXI 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames as follows: Genera…
Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Int…
Display Controller – LCD / OLED Panels (Avalon Bus)
The DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus within Altera Qs…
The demosaicing is a color filter interpolation method, and refers to an image processing algorithm for restoring full color valu…
The VID_SCALER_4K IP Core is a studio quality video scaler capable of generating scaled output images up to 216 x 216 pixels in r…
This “Dual-Core” High-Speed Baseline JPEG Encoder (Compression) core is capable of encoding video on-the-fly while producing stan…
OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
D/AVE NX is the latest and most addition to the D/AVE family of rendering cores.
Real-time Pixel Processor for Vision applications
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable Wide Dynamic Range (WDR) capable im…
Video Quality Metric Accelerator IP
Purpose-built silicon IP to accelerate compute-intensive video quality measurement such as VMAF
H.264 Audio & Video Decoder IP
The H.264 Decoder IP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA de…
Image warping IP (Distortion Correction IP)
Integrating coordinate transformation functions powered by GPU processing technologies. Distortion correction (any-shape transform), scaling, rotation.
Image warping IP (distortion correction IP)
Distortion correction (any-shape transform), mag/min scaling, rotation - Resolution: Up to 4K x 4K, RGB/YUV (8-bit)
Image codec/encoder/decoder (Customizable) - ISO/IEC 10918-1 JPEG standard
Supported Standards ISO/IEC 10918-1 JPEG standard Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pi…
The first GPU based on Arm’s 5th Gen architecture and designed for flagship smartphones.
HEVC/AVC Dual-core video encoder
HEVC/AVC Dual-core video encoder
ACAP HDR Image Signal Processing Framework
The ACAP HDR Image Signal Processing Framework is intended to showcase a logicBRICKS IP suite implementation of High-Dynamic Rang…