Video encoding with low-cost FPGAs for multi-channel H.264 surveillance
Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
Vendor:
Ocean Logic Pty Ltd
Category:
Video Processing
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
Overview
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm. The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution. Simple, fully synchronous design with low gate count.
The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm designed to decode a bitstream created by the OL_H264e core and output progressive video up to HDTV 1920x1080 at 30 fps.
Each block of 16x16 pixels is processed in just 1024 cycles. This means that each pixel is processed in just 4 cycles. Consequently, given an target video stream of resolution X by Y, and frame rate fps, the minimum clock frequency to decode a such bitstream is:
F = 4*X*Y*fps
This allows the core to process the video stream at relatively low clock frequencies. For example, HDTV video of 1920x1080 @ 30 fps requires ~250 MHz, whereas VGA video of 640x480 @ 30 fps requires ~37 MHz.
Key features
- Fully compatible with the output of the OL_H264MCE encoder core.
- Up to Profile level 4.1 can be decoded.
- Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).
- Very low operational frequency : from ~1.5 MHz for QCIF @ 15 fps to ~250 MHz for 1920x1080 @ 30 fps.
- Single core HDTV support in FPGA : 720p (1280x720) at 30 fps in high end FPGAs (Virtex4) . 4 CIF (704x576) at 30 fps in low end FPGAs.
- No CPU required for decoding.
- Very low latency decoding
- Motion vector up to –32.00/+31.75 pixels.
- Support for most of intra4x4 and all intra16x16 modes.
- Multiple slices support for better error resilience.
- Block skipping logic for lower bitrate.
- Deblocking filter for better quality.
- External memory interface tolerant of high latencies and delays, ideal in a SoC system or in a shared bus with a CPU. The memory interface can be clocked at a different frequency from the core for easier integration.
- Supports YUV 4:2:0 video output.
- Min Clock speed = 4 x the raw pixel clock speed.
- Simple, fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
Block Diagram
OL_H264MCLD block diagram
Applications
- Digital video recorders.
- Video wireless devices.
- Video surveillance systems.
- Hand held HDTV video cameras.
What’s Included?
- Synthesizable VHDL or Verilog RTL.
- Bit accurate C model.
- Complete HDL testbench.
- Complete data sheet.
Specifications
Identity
Part Number
OL_H264MCLD
Vendor
Ocean Logic Pty Ltd
Type
Silicon IP
Compute
Codec Standard
H.264 / AVC
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Australia
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Frequently asked questions about Video Processing IP
What is Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder?
Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder is a Video Processing IP core from Ocean Logic Pty Ltd listed on Semi IP Hub.
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
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