Video Processing IP cores provide hardware-accelerated video encoding, decoding, transcoding, compression, decompression, scaling, and stream processing capabilities for modern SoC and ASIC designs.
This category includes IP solutions supporting major video and image compression standards such as AV1, AV2, H.264/AVC, H.265/HEVC, H.266/VVC, VP8, VP9, MPEG-2, MPEG-4, MPEG-5 LCEVC, JPEG, and JPEG 2000. These IP cores enable efficient video delivery, storage, streaming, analytics, and multimedia processing across a wide range of semiconductor applications.
This catalog allows semiconductor engineers to evaluate and compare Video Processing IP from leading vendors based on codec support, encoding and decoding performance, video quality, resolution capability, throughput, latency, silicon area, power efficiency, and process node compatibility.
Multi-format video decoder IP Core
Hantro VC9000NanoD is a multi-format video decoder supporting all significant video standards and proprietary video formats.
Multi-format video encoder IP Core
Multi-format video encoder supporting H.264, VP8 and JPEG. It is the first HW IP encoder to support VP8 for Google’s WebM and WebRTC.
Multi-format video decoder IP Core
The VC9000D enables 8K decoding with a small silicon single-core solution, or multi-core solution up to 8K@120fps, supporting AV1…
Video Decoder IP optimized for HD use cases
D100 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers lo…
The Xilinx® LogiCORE™ IP H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoC devices is capable of performing vide…
Video Frame Buffer Read and Video Frame Buffer Write
The Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access b…
The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors,…
The Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter…
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.
The Xilinx® LogiCORE™ IP Video Mixer enables users to mix video layers.
H.264 High 10 Intra Profile Encoder
The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
Motion JPEG Over IP – HD Video Encoder Subsystem
This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of motion JPEG…
H.264 Video Over IP – HD Decoder Subsystem
This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid d…
H.264 Video Over IP – HD Encoder Subsystem
This Video Over IP Subsystem integrates H.264 compression, Transport Stream and RTP/UDP/IP encapsulation to enable the rapid deve…
The H.265 HEVC Decoder System IPr is a optimized and parameterisable IP Core targeted exclusively at Intel FPGA technology.
High Speed Low Power JPEG Codec
IP
JPEG 2000 HD encoder board, is a PCI-Express acceleration board for performing JPEG 2000 compression.
JPEG 2000 HD decoder board, is a PCI-Express acceleration board for performing JPEG 2000 decompression.
Included at no additional charge with ISE software.
Xilinx Test Pattern Generator IP Core provides convenient generation of test patterns for Video System bring up, evaluation and d…