IP
- USB 2.0
- SMIC
- 40nm
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
IP
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
SMIC 0.13um 1.2V/3.3V ONFI and MultIO combo IO
VeriSilicon SMIC 0.13μm ONFI COMBO I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing Interna…
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver.
SMIC 0.18um Mini-LVDS Transmitter
The Mini-LVDS transmitter converts up to 48-bit or 36-bit RGB parallel data into 6-pair/3-pair of Mini-LVDS data stream that can …
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial …
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
The USB11PHY is an IP version of USB transceiver.
SMIC 0.18um Low Leakage MMC Card
To provide a solution of the MMC cards, SMIC18LL_MMC_04B is integrated together by three independent IPs: SMIC18LL_PRG_03, SMIC18…
SMIC 0.18um Low Leakage MMC Card
To provide a solution of the MMC cards, SMIC18LL_MMC_04 is integrated together by three independent IPs: SMIC18LL_PRG_03, SMIC18L…
SMIC 0.18um Low Leakage MMC Card
To provide a solution of MMC cards, SMIC18LL_MMC_01 is integrated together by four independent IPs: SMIC18LL_PRG_03, SMIC18LL_ROS…