SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
- SMIC
- 65nm
- LL
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core…
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transceiver IP is a Serializer/Deserializer (SERDES) pair that transparently translates 12–bit parallel bus into serial …
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
The LVDS transmitter converts 28-bit data into 4-pair LVDS data stream.
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
The USB11PHY is an IP version of USB transceiver.
The USB1.1 PHY is an IP version of USB transceiver.
SMIC 0.18um Reduced Swing Differential Signaling Transmitter
This is an embedded bus transmitter for RSDS™ (Reduced Swing Differential Signaling) interface.
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
LVDS receiver, 650M, 5 channel
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.
Sub-LVDS receiver followed by 1:4 de-serializer
The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.
IP
SMIC 130nm G LVDS 800Mbps Transmitter
IP
SMIC 130nm G LVDS 1.25Gbps Transmitter
IP
SMIC 130nm G LVDS 1.25Gbps Receiver
IP