IEEE 802.3bj Reed-Solomon Encoder and Decoder

IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates over backplanes and copper cables for 100 Gbit/s throughput. The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.

 IEEE 802.3bj RS Decoder

 Key benefits of the decoder are:

•  High-throughput, low-latency decoder core.
•  Support for single channel mode (100 Gbit/s).
•  Support for bypass mode with low latency.
•  Symbol error measurement per lane.
•  Detection of uncorrectable code words.
•  Easy-to-use handshaking interfaces.
•  Available for ASIC and FPGAs.

IEEE 802.3bj RS Encoder

Key benefits of the encoder are:

•  High-throughput, low-latency encoder core.
•  Support for single channel mode (100 Gbit/s).
•  Easy-to-use interfaces.
•  No RAMrequired.
•  Available for ASIC and FPGAs.

 Performance Figures

•  100 Gbit/s coded throughput at 625 MHz.
•  Decoding latency of 92.8 ns at 625 MHz.
•  Latency of 1.6 ns at 625 MHz in bypass mode.
•  Bit Error Rate 10 11 at 8.8 dB (EB/N0).
•  Block Error Rate 10 8 at 8.7 dB (EB/N0).

• Compliant with IEEE 802.3bj, Clause 91
• Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
• Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols

• High-throughput, low-latency core
• Support for single channel mode (up to 100 Gbit/s)
• Support for bypass mode with low laten
• Symbol error measurement per lane
• Detection of un-correctable code words
• Block-to-block on-the-fly switching between KP4/KR4 codes
• Easy-to-use handshaking interfaces.
• No internal RAM required
• Available for ASIC and FPGAs (AMD Xilinx, Intel)
• Deliverable includes Verilog source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

• KR4 single channel
• KP4/200 g single channel
• KP4/KR4 single channel
• KP4/KR4 multi channel
• KP4/KR4/RS272 single channel
• KP4/KR4/RS272 multi channel

• VHDL or Verilog source code or synthesized netlist
• HDL simulation models e.g. for Aldec’s Riviera-PRO
• VHDL or SystemC testbench
• bit-accurate Matlab, C or C++ simulation model
• comprehensive documentation