Overview
The V68000 is a synthesizable VHDL (soft) core design which is object code compatible with Motorola's popular MC68000. The V68000 is intended to be used in system-on-a-chip applications constructed using gate-arrays or standard cells. It should be especially interesting to designers who currently use MC68000s in embedded control applications and want to integrate its functionality with other designs/peripherals/etc. onto a single chip (ASIC).
The V68000 is a fully synchronous design and contains no microcode; all control is implemented via state machines. It is written in synthesizable VHDL using IEEE standard libraries. It uses a single clock. The design has also been translated to Verilog.
The V68000 core interfaces to other on-chip periperals and memory using simple, synchronous interface. A "ring" circuit is available that converts the synchronous interface into a bus that closely resembles the MC68000 (Motorola) bus.
The V68000 has very good performance, with many instructions completing in 2 to 4 clock cycles (using 0 wait state memory). Most instructions use fewer clock cycles than the original MC68000.
The V68000 also contains debug assist hardware to provide "ICE"-like debugging access. This hardware is intended to be accessed through a JTAG port (a JTAG interface is also available).
The V68000 synthesizes to approximately 30 to 35 Kgates (this is very dependent upon the target libary) when using a typical standard cell libary. Version 3.0 of the design is currently in the test/validation process. It makes slightly different tradeoffs to allow better optimization in an FPGA environment. The design goal for this version is operation at 80 to 100 Mhz in an Altera FPGA device.
The design kit includes the synthesizable VHDL model, a sample synthesis script, a sample constraint file, a VHDL test bench, and test stimulus files. Over 2600 test sequences are included to validate instruction and address mode functionality. Instructions and a build script are also included to create a software generation environment for embedded systems using the GNU gcc tools.
VLSI Concepts can provide customization of the design, if requested.
Design and integration assistance is also available from VLSI Concepts.
Learn more about CPU IP core
For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.
The ChiPy DSL is Quadric's Python framework for building complete on-chip pipelines. Using YOLOX-M as a case study, we show how backbone inference, box decoding, and NMS run entirely on the Chimera GPNPU — no host CPU intervention, no DDR round-trips, just Python compiled to silicon.
As part of the new Arm Lumex compute subsystem (CSS) platform, the Arm C1 CPU cluster – the first built on the Armv9.3 architecture – is the next evolution of our highest performing CPU cluster for consumer devices, designed to unleash the full potential of on-device AI and elevate the user experience.
Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.
Unlock ultra-efficient performance, advanced AI processing, and robust security with the Cortex-A320—designed to power the future of IoT and edge AI innovation.
Pie maintains low computation latency, high throughput, and high elasticity. Our experimental evaluation demonstrates that Pie achieves optimal swapping policy during cache warmup and effectively balances increased memory capacity with negligible impact on computation. With its extended capacity, Pie outperforms vLLM by up to 1.9X in throughput and 2X in latency. Additionally, Pie can reduce GPU memory usage by up to 1.67X while maintaining the same performance. Compared to FlexGen, an offline profiling-based swapping solution, Pie achieves magnitudes lower latency and 9.4X higher throughput.