Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge

Key Upgrades Over Veyron V2

• 11+ SPECint2017 (rate=1) at up to 4.2 GHz
• Enhanced RISC-V standard matrix extension support alongside RVV 1.0 and scalar compute
• 24 TeraFLOPS/core of FP8 matrix compute for AI/ML acceleration, or up to 4.5 PFLOPS in a 192-core chiplet-based SiP
• Significantly higher IPC and performance-per-watt, driven by new microarchitecture innovations

Next-Level Microarchitecture: Wide Efficiency via Macro-Ops

• Macro-op optimized design:
  • Internal macro-ops encode 1–5 RISC-V instructions
  • Advanced fusion engine dynamically creates optimized macro-ops from hot instruction sequences
  • Acts much wider than it looks — macro-ops magnify effective decode width, backend capacity, and parallelism without physically increasing resources
  • Achieves high performance and power efficiency without brute-force frontend or backend scaling
• Hardware-optimized for software-transparent ILP improvements and shorter execution paths

Superscalar Execution and Predictive Throughput Architecture

• 16 execution pipelines and schedulers:
  • 5 integer, 3 load/store, 3 scalar FP, 5 vector/matrix
• 200+ scheduler entries, large resource queues and buffers
• Sophisticated branch and memory prediction engines:
  • Multiple primary and secondary branch predictors
  • Load value predictor, memory dependency and bypass prediction

Cluster Architecture and Coherency Fabric

• 32-core cluster design with 128MB L3 cache
• Upgraded high-bandwidth, low-latency coherent fabric enables efficient cluster scaling

Compute Density and AI Performance

• Unified scalar/vector/matrix execution model
• Exceptional AI compute density with FP8 matrix engine
• Optimized for inference acceleration at scale

Physical Design and Packaging

• Frequency-optimized physical implementation:
  • Semi-custom place-and-route for timing-critical logic
  • Custom standard cells and SRAM macros on advanced process node
• Support for UCIe-based D2D,
• Optional 3D stacking and direct memory attach