Designing Smarter Edge AI Devices with the Award-Winning Synopsys ARC NPX6 NPU IP
Gordon Cooper, Staff Product Marketing Manager, Synopsys Solutions Group
Vendor:
Synopsys, Inc.
Category:
NPU
ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
The new Synopsys ARC® NPX Neural Processing Unit (NPU) IP family delivers the industry’s highest performance and support for the …
Overview
The new Synopsys ARC® NPX Neural Processing Unit (NPU) IP family delivers the industry’s highest performance and support for the latest, most complex neural network models. The Synopsys ARC NPX6 NPU IP features up to 96K MACs with enhanced utilization, new sparsity features and new interconnect for scalability that address the demands of real-time compute with ultra-low power consumption for AI applications.
A single instance of the ARC NPX6 NPU IP delivers up to 250 TOPS at 1.3 GHz on 5nm processes in worst-case conditions, or up to 440 TOPS by using new sparsity features that can increase the performance and decrease energy demands of executing a neural network. Both the NPU IP and the new MetaWare MX Development Toolkit integrate connectivity features that enable implementation of multiple NPU instances to achieve up to 3,500 TOPS performance on a single SoC.
Neural Processor IP for Functional Safety
The Synopsys ARC NPX6FS NPU IP meets stringent random hardware fault detection and systematic functional safety development flow requirements to achieve up to ISO 26262 ASIL D compliance. The processors, with comprehensive safety documentation included, feature dedicated safety mechanisms for ISO 26262 compliance and address the mixed-criticality and virtualization requirements of next-generation zonal architectures.
High-Productivity Software Tools
The ARC MetaWare MX Development Toolkit includes compilers and debugger, neural network software development kit (SDK), virtual platforms SDK, runtimes and libraries, and advanced simulation models. MetaWare MX offers a single toolchain to accelerate application development and automatically partitions algorithms across the MAC resources for highly efficient processing. For safety-critical automotive applications, the MetaWare MX Development Toolkit for Safety includes a safety manual and a safety guide to help developers meet the ISO 26262 requirements and prepare for ISO 26262 compliance testing.
A single instance of the ARC NPX6 NPU IP delivers up to 250 TOPS at 1.3 GHz on 5nm processes in worst-case conditions, or up to 440 TOPS by using new sparsity features that can increase the performance and decrease energy demands of executing a neural network. Both the NPU IP and the new MetaWare MX Development Toolkit integrate connectivity features that enable implementation of multiple NPU instances to achieve up to 3,500 TOPS performance on a single SoC.
Neural Processor IP for Functional Safety
The Synopsys ARC NPX6FS NPU IP meets stringent random hardware fault detection and systematic functional safety development flow requirements to achieve up to ISO 26262 ASIL D compliance. The processors, with comprehensive safety documentation included, feature dedicated safety mechanisms for ISO 26262 compliance and address the mixed-criticality and virtualization requirements of next-generation zonal architectures.
High-Productivity Software Tools
The ARC MetaWare MX Development Toolkit includes compilers and debugger, neural network software development kit (SDK), virtual platforms SDK, runtimes and libraries, and advanced simulation models. MetaWare MX offers a single toolchain to accelerate application development and automatically partitions algorithms across the MAC resources for highly efficient processing. For safety-critical automotive applications, the MetaWare MX Development Toolkit for Safety includes a safety manual and a safety guide to help developers meet the ISO 26262 requirements and prepare for ISO 26262 compliance testing.
Key features
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
Benefits
- ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed.
- The ARChitect wizard enables drag-and-drop configuration of the core, including options for Instruction, program counter and loop counter widths
- Register file sizeTimers, reset and interrupts Byte ordering Memory type, size, partitioning, base address Power management, clock gating Ports and bus protocol Multipliers, dividers and other hardware features Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT).
- Adding/removing instructions
Specifications
Identity
Part Number
dwc_arc_npx_family
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about NPU IP core
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Gordon Cooper, Staff Product Manager, Synopsys Solutions Group
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Benchmarking an NPU at Scale
With every SDK release, Quadric automatically recompiles and re-profiles the entire model zoo across a broad sweep of hardware configurations. The results land in DevStudio for any SoC architect to explore — no sales call, no handpicked numbers.
Your NPU Learned to Listen
Whisper runs end-to-end on Chimera. Encoder and decoder compiled as native GPNPU kernels, INT4 weights, FP16 attention, top-1 token match against the float32 reference. Scales to four cores with a flag, no recompile.
Can Your NPU Run DOOM? Chimera Can.
Is your NPU DOOMed? Quadric's Chimera GPNPU runs every AI model — and a complete DOOM engine. Find out why Quadric is different.
Frequently asked questions about NPU IP cores
What is ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications?
ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications is a NPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this NPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.