Vendor: Sifive, Inc. Category: CPU

64-bit embedded processor, fully compliant with the RISC-V ISA

SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA.

RISC-V View all specifications

Overview

SiFive’s E51 Coreplex is a 64-bit embedded processor, fully compliant with the RISC-V ISA. An extremely small-footprint, low-power design makes the E51 Coreplex ideal for devices that require a tiny system controller for housekeeping, security, or host processing within a larger 64-bit SoC. An extended memory map of 40 physical address bits also makes the E51 Coreplex a great solution for SSD controllers and networking applications.

Key features

  • Fully compliant with the RISC-V ISA specification
  • RV64IMAC Support:
    • RV64I – 64-bit RISC-V with 32 integer registers
    • Integer Multiplication and Division (M) support
    • Atomic Mode (A) support for high-performance, portable software
    • Compressed Mode (C) support for better code density
  • Machine and User Mode Support
  • In-order, 5-6 stage variable pipeline
  • Advanced Memory Subsystem:
    • 16KB, 2-way Instruction Cache
    • Instruction Tightly Integrated Memory (ITIM) option
    • Up to 64KB Data Tightly Integrated Memory (DTIM) support
  • Support for up to 40 physical address bits
  • Efficient and Flexible Interrupts: Local interrupts w/ vectored addresses — up to 16
    • Platform Level Interrupt Controller (PLIC) — 511 interrupts w/ 7 priority levels
    • Coreplex Local Interrupts (CLINT) — 1 timer, 1 SW
  • 8-Region Physical Memory Protection (PMP)
  • 1.8 DMIPS/MHz
  • 2.76 Coremark/MHz

Block Diagram

E51 Coreplex block diagram

Benefits

  • RV64IAC M + U Modes
  • Up to 1.5 GHz in 28nm
  • 1.8 DMIPS/MHz
  • Physical Memory Protection (PMP)
  • 16KB Instruction Cache
  • Instruction Tightly Integrated Memory (ITIM) up to 8KB
  • Data Tightly Integrated Memory (DTIM) up to 64KB
  • 31 Usable Registers
  • 511 Global Interrupts + 16 Local Vectored Interrupts
  • No royalties
  • 7-page contract
  • Open access to all

What’s Included?

  • E51 Coreplex IP in Verilog
  • Constraints File (SDC)
  • Integration Guide covering:
    • Synthesis
    • Place and Route
    • Floorplanning
  • Test simulation environment

Specifications

Identity

Part Number
E51 Coreplex
Vendor
Sifive, Inc.
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Sifive, Inc.
HQ: USA

Learn more about CPU IP core

Introducing SKL: The SiFive Kernel Library

We’re thrilled to announce the launch of the SiFive Kernel Library or SKL (pronounced “skill”), an open-source collection of highly-optimized computational routines for the RISC-V Vector ISA (RVV) and its various extensions, including SiFive’s matrix engines.

Frequently asked questions about CPU IP cores

What is 64-bit embedded processor, fully compliant with the RISC-V ISA?

64-bit embedded processor, fully compliant with the RISC-V ISA is a CPU IP core from Sifive, Inc. listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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