L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
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Discover CPU and Microcontroller IP for embedded processing, real-time control, and general-purpose computation in semiconductor designs. This category includes processor IP used in SoCs, ASICs, and embedded platforms requiring software programmability, deterministic control, and scalable compute performance.
Compare CPU and Microcontroller IP by ISA, bit width, safety support, performance level, memory architecture, debug features, ecosystem maturity, and target applications. These IP cores are widely used in automotive, industrial, IoT, consumer, and communication chips.
L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
ARC HS68 64-bit, dual-issue processor with MMU, ARCv3 ISA, for embedded Linux applications
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
ARC HS66 64-bit, dual-issue processor core, interconnect, ARCv3 ISA, for embedded applications
The ARC® HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where hi…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS57DMP multi-core version of dual-issue HS57D ARCv3DSP ISA, with I&D cache
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS57D 32-bit, dual-issue processor core and interconnect, ARCv3DSP ISA, with I&D cache
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
ARC HS56 32-bit, dual-issue processor core & interconnect, ARCv3 ISA, for embedded applications
The ARC® HS56, HS57D and HS58 processors feature a dual-issue, 32-bit superscalar architecture for use in embedded applications w…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
ARC HS46FS with ASIL B / ASIL D support, including lock-step for functional safety applications
The ARC® HS46FS, HS46FSx4, HS47DFS, HS47DFSx4, HS48FS, and HS48FSx4 functional safety processors (ARC HS4xFS) simplify developmen…
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…
ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
The DSP-enhanced ARC® EMxD and HS4xD Families of embedded 32-bit processors are based on the scalable ARCv2DSP Instruction Set Ar…