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Vendor:
ChipCraft
Category:
CPU
32-bit High Performance Single/Multicore RISC Processor
The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor.
Overview
The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The core is interfaced using the AMBA AHB, AHB-Lite and APB buses. The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
Key features
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
- Up to 1.37 DMIPS/MHz/Core
- Up to 2.29 CoreMark/MHz/Core
- Optional set-associative caches with data snooping
- Power-down mode
- On-chip debug support
- FPGA and silicon proven
- JTAG or 2-pin Serial Wire Debug
Block Diagram
CC100-C block diagram
Benefits
- Synthesizable RTL Verilog source code
- Cycle accurate simulator
- Custom instruction set extension
- Mature free GNU-Based C/GDB toolchain
- Full implementation and maintenance support with individual approach
- Low-cost and flexible licensing
- Embedded solution for low-power and low-footprint applications
- Suitable for mobile, IoT and wearable devices
Specifications
Identity
Part Number
CC100-C
Vendor
ChipCraft
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
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Frequently asked questions about CPU IP cores
What is 32-bit High Performance Single/Multicore RISC Processor?
32-bit High Performance Single/Multicore RISC Processor is a CPU IP core from ChipCraft listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.