Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Roa Logic BV
Category:
CPU
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
The RV12 is a configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market.
Overview
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set.
The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Optional features include Branch Prediction, Instruction Cache, Data Cache, and Debug Unit. Parameterised and configurable features include the instruction and data interfaces, the branch-prediction-unit configuration, and the cache size, associativity, and replacement algorithms. Providing the user with trade offs between performance, power, and area to optimize the core for the application
Key features
- High Performance 32/64bit CPU
- Royalty Free Industry standard instruction set (www.riscv.org)
- Parameterized 32/64bit data
- Fast, precise interrupts
- Custom instructions enable integration of proprietary hardware accelerators
- Single cycle execution
- Optimizing folded 4-stage pipeline
- Optional/Parameterized branch-prediction-unit
- Optional/Parameterized caches
- Highly Parameterized
- User selectable 32 or 64bit data
- User selectable Branch Prediction Unit
- User selectable hardware multiply-divide (M extension)
- User selectable instruction and/or data caches
- User selectable cache size, structure, and architecture
- Flexible bus architecture supporting AHB, Wishbone, AXI, ...
- Size and power optimized design
- Fully parameterized design provides power/performance tradeoffs
- Small silicon footprint; 30kgates for full featured implementation
- Industry standard software support
- Eclipse IDE for Windows/Linux
- GNU Compiler Collection, debugger, linker, assembler
- Architectural simulator
Block Diagram
RV12 - 32/64 bit, Single Core CPU block diagram
What’s Included?
- Full Source Code
- Testbenches
- Compilation Scripts
- Documentation
Specifications
Identity
Part Number
RV12 - 32/64 bit, Single Core CPU
Vendor
Roa Logic BV
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
The Netherlands
Learn more about CPU IP core
Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era
For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
The ChiPy DSL is Quadric's Python framework for building complete on-chip pipelines. Using YOLOX-M as a case study, we show how backbone inference, box decoding, and NMS run entirely on the Chimera GPNPU — no host CPU intervention, no DDR round-trips, just Python compiled to silicon.
Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
As part of the new Arm Lumex compute subsystem (CSS) platform, the Arm C1 CPU cluster – the first built on the Armv9.3 architecture – is the next evolution of our highest performing CPU cluster for consumer devices, designed to unleash the full potential of on-device AI and elevate the user experience.
Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.
Introducing Cortex-A320: Ultra-efficient Armv9 CPU Optimized for IoT
Unlock ultra-efficient performance, advanced AI processing, and robust security with the Cortex-A320—designed to power the future of IoT and edge AI innovation.
Frequently asked questions about CPU IP cores
What is RISC-V Processor - RV12 - 32/64 bit, Single Core CPU?
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU is a CPU IP core from Roa Logic BV listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.