Vendor: T-Head Category: CPU

Energy-efficient 32-bit superscalar processor

C807 utilizes an 8-stage pipeline and dual-issue superscalar architecture, with a standard memory management unit, and can run Li…

Overview

C807 utilizes an 8-stage pipeline and dual-issue superscalar architecture, with a standard memory management unit, and can run Linux and other operating systems.

Key features

  • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
  • Pipeline: 8-stage;
  • Microarchitecture: Dual-issue, lightweight, out-of-order;
  • General register: 32 32-bit GPRs;
  • Cache: I-cache: 16 KB/32 KB/64 KB (size options); D-cache: 16 KB/32 KB/64 KB (size options);
  • Bus interface: Dual bus (system bus + peripheral bus);
  • Memory protection: On-chip memory management unit supports hardware backfilling;
  • Floating point engine: Supports single and double precision floating point operations;
  • Lightweight out-of-order execution: Lightweight out-of-order execution architecture based on a distributed reservation station to improve instruction-level parallelism;
  • architecture based on a distributed reservation station to improve instruction-level parallelism
  • Low power cache access: Cache access filter to reduce the power consumption during operation;
  • Hybrid branch processing: Hybrid processing technology including branch direction, function return address and indirect jump address prediction to improve fetching efficiency.

Block Diagram

Applications

  • Smart Home Appliances;
  • Industrial Control.

Specifications

Identity

Part Number
C807
Vendor
T-Head
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: China

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Frequently asked questions about CPU IP cores

What is Energy-efficient 32-bit superscalar processor?

Energy-efficient 32-bit superscalar processor is a CPU IP core from T-Head listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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