Vendor: T2M GmbH Category: Modulation Demodulation

DVB-S2/S Demodulator and Decoder IP (Silicon Proven)

The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips.

Overview

The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips. It contains tuner Rx gain control which makes PDM Demodulator a high performance (A)PSK output Rx at AGC. Further stages of gain control are demodulator core intended for DVB-S2 and DVB-S implemented digitally within the demodulator. forward link applications. The demodulator is compatible with the ACM, VCM, and CCM configurations of the DVB-S2 Standard including DVB-S extensions and is therefore suitable for the reception of DVB broadcast, DSNG, professional and broadband interactive services.

DVB-S and S2 demodulation:
Compliant with ETSI EN300421 and EN302307
Symbol rates from 1 to 45 Ms/s
Enhanced FEC for DVB-S and DirecTV legacy transmissions

Key features

  • Compatible with all ACM (Adaptive Coding and Modulation), VCM (Variable Coding and Modulation) and CCM (Constant Coding and Modulation) configurations of ETSI EN 302 307-1 and ETSI EN 302 307-2.
  • Frame-by-frame selection of frame size, FEC code rate and modulation format (QPSK, 8PSK, 16APSK and 32APSK).
  • Support for DVB-S2 extensions (S2X) FEC code-rates and modulation formats (64APSK, 128APSK and 256APSK)
  • Support for an arbitrary range of symbol rates up to 40% of the master clock frequency
  • Two-stage, stepped carrier search provides wide acquisition range
  • Integrated, high-performance pi/2-BPSK demodulator and Reed Muller FEC decoder for Frame Header processing (PLSCODE).
  • Baseband I/Q radio interface incorporating compensation for DC offset and quadrature imbalances
  • Pilot-assisted carrier tracking ensures robust performance in the presence of high levels of phase noise.
  • PL sync acquisition and maintenance at – 2dB SNR (Es/N0)
  • Digital decimation and channel filters reject up to +10dBc of adjacent channel interference.
  • Fully-digital carrier and clock recovery circuits eliminate the need for an external VCXO.
  • Compatible with leading LDPC FEC decoder solutions.
  • Supplied as a protected bitstream or netlist (Megacore® for Altera® FPGA targets).

Block Diagram

Benefits

  • Silicon Proven IP Core
  • Extracted from Production Chips
  • Multiple applications
  • Modification rights, unlimited usage
  • Ready to License
  • Fully Packaged
  • Modifications Rights

Applications

  • STB SOC
  • TV SOC
  • PCTV Dongle etc

What’s Included?

  • Verilog Source RTL Code plus Simulation Environment
  • C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers

Specifications

Identity

Part Number
DVB-S2/S Demodulator & Decoder IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Germany

Learn more about Modulation Demodulation IP core

Three Major Inflection Points for Sourcing Bluetooth Intellectual Property

Synopsys is now shipping support for Bluetooth® 5.4, the latest specification from the Bluetooth SIG (Special Interest Group). The enhancements in Bluetooth 5.4 will open additional markets and use cases. This is one of the many inflection points in the Bluetooth Low Energy market that will be discussed in this paper.

Part 2: Opening the 5G Radio Interface

Carriers are now deploying 5G across the globe driven by the need to keep up with relentless mobile data growth. 5G New Radio (NR) operates at higher frequencies to increase bandwidth, but at the expense of range. There will therefore be a need for a much larger number of 5G RUs to provide the same coverage. The availability of cost-effective, reliable and open 5G radio units is therefore critical.

An Integrated, Tunable RF Filter: an Enabler for Reconfigurable Front-Ends

This paper presents the design and performance of a key RF circuit necessary for the realization of a reconfigurable, integrated RF front-end: a tunable frequency, selectable bandwidth, on-chip, “SAW replacement” filter. The on-die tunable filter presented here has a tunable center frequency up to 1 GHz, a selectable bandwidth up to 40 MHz, and an adjacent channel rejection down to 60 dB.

Design considerations for integrated CMOS receivers

To meet the demands for the multi-band, multi-mode wireless standards in the current market, a highly integrated wireless receiver (RX) is desired. CMOS technology has become the technology of choice for the integrated receiver design.

Silicon IP for Programmable Baseband Processing

An efficient IP reuse strategy relies on IP blocks with wide applicability. That makes generic blocks, such as programmable processors preferable. However, in many applications such as handheld wireless terminals, additional silicon area and power consumption compared to fixed function solutions can not be accepted.

Frequently asked questions about Modulation and Demodulation IP cores

What is DVB-S2/S Demodulator and Decoder IP (Silicon Proven)?

DVB-S2/S Demodulator and Decoder IP (Silicon Proven) is a Modulation Demodulation IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Modulation Demodulation?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Modulation Demodulation IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP