Generic Polar FEC Encoder and Decoder

Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communications, which exhibit a particularly high performance while requiring a low-complexity implementation. They were first adopted by the 3GPP 5G NR standard.

The Polar Encoder IP core is a scalable solution featuring code-rate flexibility, high throughput and very low latency on state-of-the-art FPGAs. Since a polar encoder normally requires information data to be presented in a certain way at its input, the Creonic Polar Encoder IP takes care of this in a pre-encoding stage.This important feature, with aid of AXI4-Stream interface ports, allows a very straight-forward integration of the core into any system.

• Fully-pipelined architecture
• Support for systematic and non-systematic encoding
• Support for coded block lengths of up to 1024 bits
• Support for a wide variety of
• code-rates (1/8, 1/4, 3/8, 1/2, 5/8, 3/4, 13/16, 7/8)

• Easy design-time parameterization of block length and supported code rates, for adjustment of resource utilization
• On-the-fly configuration of the code-rate on a block-by-block basis
• Does not require an extra IP to prepare the input data for encoding
• High code-rate granularity
• AXI4-Stream for easy integration
• Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip)
• Deliverable includes VHDL source code or synthesized netlist, HDL simulation models (e.g. for Aldec’s RivieraPRO), VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

• Satellite communication
• Wireless communication
• Applications with highest demands on forward error correction
• Applications with the need for a wide range of code rates

• VHDL source code or netlist
• HDL simulation models, e.g. for Aldec’s RivieraPRO
• VHDL testbench
• bit-accurate Matlab, C or C++ simulation model
• comprehensive documentation