LDPC Encoder / Decoder for 5G and 6G NTN PHY

AccelerComm's LDPC IP cores deliver flight-proven FEC performance for 5G and 6G NTN PHY designs. Built on advanced decoding algorithms developed from decades of academic research at the University of Southampton, they provide the error-correction performance that demanding satellite and terrestrial PHY workloads require.

AccelerComm LDPC provides licensable, 3GPP-compliant encoder and decoder IP cores optimised for terrestrial, transparent NTN, and regenerative satellite PHY architectures. Its high-throughput, low-latency design is FPGA- and ASIC-ready, with area-efficient implementations suited to SWaP-constrained satellite payloads and high-density ground infrastructure alike.

Already deployed in orbit on more than 200 commercial satellites, AccelerComm's LDPC IP brings a level of flight heritage that few physical layer vendors can offer. For programme teams designing 5G or 6G NTN systems where link efficiency and error-floor performance are critical, it provides a standards-based foundation that de-risks PHY development from the outset.

Flight-proven FEC at commercial scale

AccelerComm's LDPC IP has been validated in orbit on more than 100 satellites — giving PHY design teams a proven, low-risk foundation rather than an unvalidated starting point.

Up to 10x performance improvement over software-based LDPC

Hardware-optimised IP cores deliver a step-change in throughput and power efficiency compared to software implementations, reducing cost-per-bit across both payload and ground deployments.

1 dB uplink sensitivity gain

Advanced decoding techniques unlock a measurable link margin improvement, enabling higher throughput, smaller terminals, or extended coverage from the same infrastructure.

Ultra-low BLER — no error-rate floors

AccelerComm's algorithms eliminate the error-rate floors seen in conventional decoders, delivering consistently reliable performance across the full range of channel conditions.