Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
Faststream Technologies
Category:
Filters Transforms
DIGITAL UP CONVERSION (DUC)
An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC.
Overview
An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC. A lowpass interpolator, halfband interpolator, CIC compensation interpolator, CIC interpolator, and CIC gain correction comprise the filter chain.
Because sample rates are lower at the beginning of the chain, the earlier filters can maximize resource use by sharing multipliers. The CIC compensation interpolator improves the spectral response by accounting for later CIC droop when interpolating by two. For cell search and master information block recovery, LTE receivers typically employ a sampling rate of 1.92 Msps.
Because sample rates are lower at the beginning of the chain, the earlier filters can maximize resource use by sharing multipliers. The CIC compensation interpolator improves the spectral response by accounting for later CIC droop when interpolating by two. For cell search and master information block recovery, LTE receivers typically employ a sampling rate of 1.92 Msps.
Key features
- 70 MHz IF, 2.5.8, & 22MHz BWs (3dB)
- 204.8 MHz DAC Sample Rate
- The modem provides a 25 kHz fine-tune step
- Receiver / Exciter minimum freq step = 0.5 MHz, settling time < 100 us to 100Hz
- Basebang samples are converted to 70 MHz “digital IF”
- Polyphase filter approach reduces required 204.8 Msps processing to the simple data transfer
- 208.8 Msps DAC sample rate required to reduce DAC sinx/x roll-off
- The final 2x interpolation process employs parallel FIR filters that process at a 1x rate
- As a result of the quarter-wave frequency shift, the number of filter taps is reduced by a factor of two
- Maintain 16 bits in/out of DDC
- Complex mixer functions should keep 18 bits at the input and truncate to 16 bits at the output
- DUC share a single DDS FPGA instantiation
- DUC shares the same FPGA filter structures
Block Diagram
FST-DUC block diagram
Specifications
Identity
Part Number
FST-DUC
Vendor
Faststream Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Filters Transforms IP core
No size fits all for signal processing on FPGA (RF Engines)
No size fits all for signal processing on FPGA (RF Engines)
Employing general-purpose processors for radio DSP
Employing general-purpose processors for radio DSP
Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design
Finally a Practical ''Do and Don't'' primer on architecting FPGA solutions for DSP design. With more do's than don’ts, the article is a down-to-basics look at how to avoid the pitfalls and realize device benefits
10 FPGA Design Techniques You Should Know
Regardless of whether you are using VHDL, System Verilog, or a different design capture language, there are a number of universal design techniques with which FPGA engineers should be familiar, from the very simple to the most advanced.
How to implement double-precision floating-point on FPGAs
The real results of a double-precision matrix multiply core that can easily be extended to a full DGEMM benchmark are demonstrated.
Frequently asked questions about Filters and Transforms IP cores
What is DIGITAL UP CONVERSION (DUC)?
DIGITAL UP CONVERSION (DUC) is a Filters Transforms IP core from Faststream Technologies listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.