Polar Encoder / Decoder for 5G NR control channels

AccelerComm's Polar IP delivers the complete 3GPP-compliant encoding and decoding chain for 5G NR control channels. Its unique architecture enables higher degrees of parallel processing than conventional Polar implementations, significantly reducing resource and memory usage while delivering excellent BLER performance across PUCCH, PUSCH, PDCCH and PBCH.

The Polar core uses PC- and CRC-aided Successive Cancellation List decoding to achieve compromise-free error correction performance. Parallelism, latency, throughput and decoder list size are all configurable at synthesis time - including reducing list size below the standard list 8 - giving programme teams precise control over the power and performance trade-off for each target application.

Every component of the encoding and decoding chain is tightly integrated, reducing silicon area and latency without adding integration complexity. The interface is deliberately minimal: only the number of uncoded bits and encoded bits are required as inputs alongside the data. Standard AXI interfaces, MATLAB and C models, and FPGA and ASIC-optimised implementations mean the path from evaluation to production is as short as it can be.

AccelerComm Polar covers the complete encoding and decoding chain — from CRC encoding and frozen bit insertion through rate matching, channel interleaving, and PC/CRC-aided decoding — fully compliant with 3GPP TS38.212 across the full range of block sizes.

Polar coding governs every 5G NR control channel. The quality of the Polar implementation at the heart of a PHY design determines how reliably that system performs at the edges of coverage, under interference, and at the limits of link budget. AccelerComm's unique parallel architecture and PC/CRC-aided SCL decoding approach have been refined through direct engagement with 5G NR and 6G NTN standards development, and validated in production across terrestrial chipmakers, RAN vendors, and satellite programmes. MATLAB and C models are available for early evaluation, and AccelerComm's engineering team works alongside customers from first integration through to production sign-off.

Compromise-free error correction from PC/CRC-aided SCL decoding

• AccelerComm's Polar core applies PC- and CRC-aided Successive Cancellation List techniques to achieve error correction performance at the ceiling of what 3GPP allows — with no trade-off between coding gain and implementation efficiency.

Unique parallel architecture — more throughput, less silicon

• AccelerComm's Polar architecture enables higher degrees of parallel processing than conventional implementations, delivering significantly reduced resource and memory usage while maintaining excellent BLER performance in both FPGA and ASIC targets.

Fully configurable at synthesis time

• Parallelism, latency, throughput and decoder list size can all be tuned at synthesis, including reducing list size from the standard list 8 to match the exact requirements of each application — whether a power-constrained satellite payload or a high-throughput base station.

Minimal interface — fast to integrate, complete by design

• The entire Polar chain defined in 3GPP TS38.212 is implemented in a single tightly integrated IP block. With only block size parameters required as inputs and standard AXI interfaces throughout, integration effort is minimised and time to first silicon is reduced.