Vendor: AccelerComm Limited Category: Channel Coding

PDSCH Encoder for 3GPP 5G NR

3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used f…

Overview

3GPP compliant coding and modulation for Downlink Physical Shared Channels

The Physical Downlink Shared Channel (PDSCH) is used for downlink data which is shared from the gNB between time and frequency. This channel contains user equipment control messages, downlink user data and system information. The PDSCH channel needs to be designed with flexibility in mind to support various modulation and coding schemes.

AccelerComm’s family of integrated 5G NR channel products, namely PDSCH Encoder and PUSCH Decoder. On this page we detail the PDSCH Encoder which provides Forward Error Correction (FEC) encoding and decoding capabilities along with the complete Quadrature Amplitude Modulation (QAM) modulation and demodulation functionality for downlink data processing in a gNB/base station.

* This IP is implemented as per the latest 3GPP specifications and are compliant with TS 38.211 and 38.212.
* The new QAM modulator functionality complements the existing high performance AccelerComm LDPC and Polar encoder/decoder solutions.
* Like all AccelerComm IP the LDPC and modulator is configurable to several different parallelisms to optimise for SWaP (Size, Weight & Power) of each integration.

Key features

  • The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
  • PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
  • PDSCH encoder has a configurable IQ parallelism for improved performance per clock.
  • The functions included are CRC, Segmentation, LDPC encode, Rate matching, Integrated HARQ, Concatenation, Scrambling and Modulation.
  • The tight AccelerComm integration and configurability leads to optimal SWaP solutions.
  • This 5G channel IP is delivered as RTL and can be synthesised for FPGA & ASIC target devices.

Block Diagram

PDSCH Encoder block diagram

Benefits

  • Complete implementation of the relevant 3GPP standard
  • Improved BLER for UCI control data
  • Pre integrated with AccelerComm LDPC transport block encoder chains and inherits all the benefits from these
  • Single control interface
  • Supported across FPGA and ASIC platforms
  • Highly configurable for a wide range of base station (gNB) applications
  • Configurable to support maximum throughputs and minimum timing requirements for all numerologies
  • Very low latency – meets strictest requirements for uRLLC
  • Efficient design – saves device area
  • Easy to integrate using industry standard AXI interfaces

Applications

  • 5G NR Infrastructure
  • 5G gNodeB

What’s Included?

  • RTL
  • C/Matlab Models
  • Test bench

Specifications

Identity

Part Number
PDSCH Encoder
Vendor
AccelerComm Limited
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Channel Coding IP core

Frequently asked questions about Channel Coding IP cores

What is PDSCH Encoder for 3GPP 5G NR?

PDSCH Encoder for 3GPP 5G NR is a Channel Coding IP core from AccelerComm Limited listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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