What is DVB-S2 LDPC BCH Decoder and Encoder?
DVB-S2 LDPC BCH Decoder and Encoder is a Channel Coding IP core from Global IP Core Sales listed on Semi IP Hub.
Vendor:
Global IP Core Sales
Category:
Channel Coding
DVB-S2 LDPC BCH Decoder and Encoder
The DVB-S2 LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
Overview
The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
Key features
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Soft decision decoding
- BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
- ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
- Long and short frame lengths
- No error floor to QEF in Standard
- Easy to integrate within receiver
- All code rates and modulation orders
- Wideband support
Benefits
- Improved performance
- Improved efficiency w.r.t. Shannon’s limit
- Very high data rate
Applications
- DVB-S2
What’s Included?
- Synthesizable Verilog
- System Model (Matlab)
- Verilog Test Benches
- Documentation
Specifications
Identity
Part Number
DVB S2 LDPC BCH Decoder and Encoder
Vendor
Global IP Core Sales
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Frequently asked questions about Channel Coding IP cores
How should engineers evaluate this Channel Coding?
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Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.