The IPrium-DVB-C-Modulator IP Core is 32-channel DVB-C Modualtor with MAX5861 (MAX5862) support.
- Modulation Demodulation
- Silicon proven
- Now
- ETSI EN 300 429
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The IPrium-DVB-C-Modulator IP Core is 32-channel DVB-C Modualtor with MAX5861 (MAX5862) support.
1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.
10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
Half Precision IEEE-754R complete FPU for graphics processing
The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…
CCSDS (8160,7136) LDPC Decoder
The LCD01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control decoder.
CCSDS (8160,7136) LDPC Encoder
The LCE01C is a fully compatible CCSDS rate 223/255 (8160,7136) LDPC error control encoder.
Aurora-like 8b/10b @3Gbps for ALTERA Devices
REFLEX CES introduces the industry’s first release of its Aurora-‐like IP Core based on ALTERA FPGA enabling interoperability be…
Floating-point to Fixed-point Converter
Converts 32-bit floating-point numbers to fixed-point representation.
Fixed-point to 32-bit floating-point converter
FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 3…
32-bit Floating-point Divider IP Core
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard.
N-channel Multiplexed FIR Filter
FIR_NTAP_MUX is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limit…
IIR Filter Second-Order-Section
2nd order IIR filter sometimes referred to as a 'bi-quad'.
Half-band Nyquist Decimation Filter
FIR_DEC_N is a polyphase decimation filter that permits the down sampling of an input signal by any power of 2.
Generic high-speed FIR Filter with symmetry
FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps.
Generic ultra-speed FIR Filter
FIR filter designed for very high sample rate applications up to 600 MHz.
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system.
DVB-RCS and IEEE 802.16 WiMAX turbo encoder
This is an 8 state DVB-RCS and IEEE 802.16 WiMAX compatible parallel concatenated turbo encoder.