Half-band Nyquist Decimation Filter

FIR_DEC_N is a polyphase decimation filter that permits the down sampling of an input signal by any power of 2. The filter core is organized as a highly optimized systolic array, allowing the user to specify very large decimation factors while keeping resource costs to a minimum.

Input data is sampled on the rising clock-edge of clk when en is active high. Internally, the samples are filtered and decimated then presented at the output interface, y_out.

The output signal en_out is the output clock-enable signal that indicates when an output sample is valid. For instance, when decimating by a factor of 2, then en_out will have a duty cycle of 50% relative to the input clock-enable signal. When decimating by a factor of 4, the duty cycle will be 25% and so on.

• Synthesizable, technology independent VHDL Core
• Half-band polyphase decimation filter with a configurable decimation factor from 2 to 2^N
• FIR filter core implemented as an optimized 48-tap systolic array (24-taps per phase) for ultimate speed and minimal resource use
• Configurable data and coefficient widths
• Symmetric arithmetic rounding limits DC-bias problems
• Saturation of output samples - no wrap
• Ships with 14-bit coefficients giving 80 dB stop-band attenuation
• Only 12 H/W multipliers used per decimate-by-2 stage
• Supports input sample rates of up to 300 MHz+

• Decimation of signals after digital-down-conversion
• Decimation by a wide range of factors from 2 to 2N
• Reduction of input sample rate to make subsequent signal processing easier