Vendor: Advanced Architectures Category: FPU

Half Precision IEEE-754R complete FPU for graphics processing

The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…

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Overview

The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754R Standard). It is designed to provide a powerful floating-point functionality for low-power, low frequency applications.

The A2FH supports half precision operations in a 1- stage execution pipeline. The pipeline insures maximum performance in low-frequency applications, providing up to 200 MFLOPS on a 0.13u ASIC process. The host interface is clean and versatile, simplifying the interfacing to host processor pipelines.

IEEE-754R Compliance

The A2FH is designed to provide a powerful floating-point capability while minimizing die size cost. To minimize unnecessary design size, some of the rarely used features of the IEEE specification are not implemented directly in the hardware design. The following IEEE-defined operations are not directly supported in A2FH hardware, but can be supported with software support:

  • Gradual Underflow
  • Denormal Numbers

In place of gradual underflow, the A2FH implements a flush-to-zero approach when underflow occurs. This feature allows the A2FH to maintain a one-cycle throughput in all operand cases, and minimizes design size.

Optional Divide Unit

The divide unit within the A2FH design provides divide, square root, and remainder functions. In order to further minimize the design size, the A2FH can be synthesized with or without a divide unit. Many multi-media applications can be implemented without the use of divide functions. For customers who need the absolute minimum area, this option is a must.

Key features

  • Fully Synthesizable RTL - Verilog 
  • IEEE 754R compliant (except underflow)    
  • Flag outputs support conditional branching or  conditional execution
  • Supports all IEEE rounding modes
  • Supports all IEEE Exception flags 
  • Half Precision instructions
  • Single Stage Pipeline  
  • Control / Status Registers
  • Masked / Unmasked Exception control 

Block Diagram

A2FH block diagram

What’s Included?

  • verilog RTL and Testbench

Specifications

Identity

Part Number
A2FH
Vendor
Advanced Architectures
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Advanced Architectures

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Frequently asked questions about FPU IP cores

What is Half Precision IEEE-754R complete FPU for graphics processing?

Half Precision IEEE-754R complete FPU for graphics processing is a FPU IP core from Advanced Architectures listed on Semi IP Hub.

How should engineers evaluate this FPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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