Vendor: Zipcores Electronic Systems Engineering S.L. Category: Arithmetic Units

Fixed-point to 32-bit floating-point converter

FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 3…

Overview

FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 32-bit bit floating-point number at the output.

Key features

  • Key Design Features
  • Synthesizable, technology independent VHDL Core
  • Signed fixed-point or integer input
  • 32-bit floating-point output
  • Configurable word and fraction width up to 32 integer bits and 23 fraction bits
  • IEEE 754 compliant
  • High-speed fully pipelined architecture
  • 2 clock-cycle latency

Block Diagram

Applications

  • Floating-point pipelines and arithmetic units
  • Floating-point processors
  • Interfacing between floating-point and fixed-point number  systems

Specifications

Identity

Part Number
FIXED_TO_IEEE
Vendor
Zipcores Electronic Systems Engineering S.L.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about Arithmetic Unit IP cores

What is Fixed-point to 32-bit floating-point converter?

Fixed-point to 32-bit floating-point converter is a Arithmetic Units IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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