Vendor: Zipcores Electronic Systems Engineering S.L. Category: Arithmetic Units

Floating-point Adder

High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.

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Overview

High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard. Results have a latency of 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.

Key features

  • Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
  • Supplied as human readable VHDL (or Verilog) source code
  • 32-bit floating-point arithmetic
  • IEEE 754 compliant1
  • High-speed fully pipelined architecture
  • Only 4 clock-cycles of latency

Block Diagram

IEEE_ADD block diagram

Applications

  • Floating-point pipelines and arithmetic units
  • Floating-point processors

Specifications

Identity

Part Number
IEEE_ADD
Vendor
Zipcores Electronic Systems Engineering S.L.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Zipcores Electronic Systems Engineering S.L.

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Frequently asked questions about Arithmetic Unit IP cores

What is Floating-point Adder?

Floating-point Adder is a Arithmetic Units IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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