BCH codes are widely used where bit errors are scattered randomly within the codeword.
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
BCH codes are widely used where bit errors are scattered randomly within the codeword.
ITU 25G PON LDPC Encoder and Decoder
The common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks is defined as part of the FEC in the …
LDPC Encoder/Decoder for Flash controller
The LDPC IP is a Low-density parity-check code encoder and decoder designed for 3D NAND Flash error correction to address the rel…
This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards.
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications.
DVB-S2 LDPC BCH Decoder and Encoder
The DVB-S2 LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
The DVB-S2X LDPC Decoder is a FEC core decoder for Digital Video Broadcasting via Satellite.
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard.
Multi-Channel Signature Calculator
IP
DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
The AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel.
5G NR is the mobile broadband standard of the 5th generation.
Generic Polar FEC Encoder and Decoder
Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communicati…
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
The Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying inp…
CCSDS AR4JA LDPC Encoder & Decoder
The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
LTE and LTE (LTE-A) are the mobile broadband standard of the 4th generation.
Single precision fixed-size streaming floating-point FFT
This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.