Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
IEEE 802.11n/ac/ax Encoder and Decoder
The IPrium-LDPC-802.11-WIFI-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm…
CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B.
Key Value Store/Exact Match Search Engine
The Ultra-Low-Latency (ULL) Exact Match Search Engine (EMSE) IP is latency-optimized Key-Value Store (KVS) system for Accelerated…
CCSDS SCCC Modulator/ Turbo Encoder
CCSDS SCCC Modulator/ Turbo Encoder
The LCE02C is a high speed encoder for the CCSDS telemetry (TM) accumulate, repeat by four, jagged accumulate (AR4JA) low density…
CCSDS Rate 1/2 TC and TM LDPC Decoder
The LCD03C is a low complexity decoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
CCSDS Rate 1/2 TC and TM LDPC Encoder
The LCE03C is a low complexity encoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
Power and area optimised Bitcoin miner engine
The eSi-BTC core is a Bitcoin miner engine that perform double SHA256 Hash.
The demand for high-speed data connection services develops in tandem with the number of internet users and multimedia apps.
multiple users and data streams must be processed concurrently in a contemporary communication system based on existing 4G and fu…
Quadrature Amplitude Modulation: Modulator and Demodulator
QAM Modulator and Demodulator combine two amplitude modulation signals into a single data transfer channel: 1.
Crest Factor Reduction IP Core
Crest Factor Reduction (CFR) is a technique for lowering a waveform’s power ratio from higher to average.
DVB-RCS2 Turbo Decoder and Encoder
On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive S…
Digital Predistortion (DPD) IP Core
The next fifth-generation (5G) wireless networks promise connection speeds and data rates that are 100 times faster than current …
The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…
Versatile, Ultra-Low-Power DSP for Audio, Voice, Vision, and AI
Smallest, ultra-low-energy DSP for always-on sensor fusion, always-listening voice trigger, and Bluetooth/BLE codecs The Cadence®…
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The LDPC Error Correction Core (Alcyone) delivers industry- error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Fl…
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…