Vendor: WASIELA Category: Channel Coding

ISDB-S3-LDPC-BCH Decoder

ISDB-S3-LDPC-BCH Decoder

Key features

  • Layered Decoding
  • Minimum sum algorithm
  • Soft decision decoding
  • BCH decoder works on GF (2^16 ) and corrects up to t =12 errors
  • ARIB STD-B44 2.0 standard compliant
  • The code length Nldpc is 44880 bits for all the supported code rates

Benefits

  • Low-power and low-complexity design
  • LDPC decoder, Energy dispersal and BCH decoder
  • Frame-to-frame on-the-fly configuration
  • Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation

Specifications

Identity

Part Number
ISDB-S3-LDPC-BCH Decoder
Vendor
WASIELA
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Egypt

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

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Frequently asked questions about Channel Coding IP cores

What is ISDB-S3-LDPC-BCH Decoder?

ISDB-S3-LDPC-BCH Decoder is a Channel Coding IP core from WASIELA listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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