The CORDIC IP provides hardware acceleration of mathematical functions (mainly trigonometric ones) commonly used in motor control…
- Arithmetic Units
Arithmetic Unit IP cores provide hardware acceleration for core mathematical operations in modern SoC and ASIC designs.
These IP cores implement datapath functions such as multiply-accumulate, division, square root, and specialized numeric pipelines used throughout compute and signal-processing systems
This catalog allows you to compare Arithmetic Unit IP cores from leading vendors based on throughput, latency, area efficiency, and process node compatibility.
Whether you are designing DSP subsystems, AI accelerators, control systems, or high-performance datapaths, you can find the right Arithmetic Unit IP for your application.
The CORDIC IP provides hardware acceleration of mathematical functions (mainly trigonometric ones) commonly used in motor control…
The FastMath Pack is a math processing accelerator for the ARC HS family
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
PNU is a stand-alone Coprocessor capable of doing real-number computation on posit operands.
The Divider IP core is a one-clock divider which completes one integer division every clock.
CORDIC (COordinate Rotation DIgital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric funct…
The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third ope…
The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is adde…
Included with Xilinx ISE Software The Multiplier Accumulator IP core product is a parallel multiplier accumulator module that per…
The multiplier operation is essential and abundant in DSP Applications.
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
The Xilinx LogiCORE™ CORDIC IP implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially deve…
The Xilinx LogiCORE™ Complex Multiplier IP core implements AXI4-Stream compliant, high-performance, optimized complex multipliers…
The Adder/Subtracter IP provides LUT and single DSP48 slice add/sub implementations.
The Accumulator IP provides LUT and single DSP48 slice accumulation implementations.