Vendor: Xilinx, Inc. Category: Arithmetic Units

Multiplier Accumulator

Included with Xilinx ISE Software The Multiplier Accumulator IP core product is a parallel multiplier accumulator module that per…

Overview

Included with Xilinx ISE Software

The Multiplier Accumulator IP core product is a parallel multiplier accumulator module that performs fixed or programmable-length accumulations. The core's A and B inputs use unsigned or signed data of up to 32 bits wide. The core has selectable pipeline levels. It offers truncation and rounding of the multiplier output. The core also has an accumulation saturation option, optional carry in, carry out, overflow pins, and input/output registers.

Key features

  • Parallel multiply accumulator module.
  • Signed or Unsigned inputs parameterizable up to 32-bits.
  • Automatic optimization for speed.
  • Parameterizable rounding modes or output.
  • Support for saturation.

Specifications

Identity

Part Number
Multiplier Accumulator
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Arithmetic Units IP core

Implementing matrix inversions in fixed-point hardware

We implement fixed-point matrix inversion on a Virtex-4 FPGA using a synthesizable QR-decomposition MATLAB model and the AccelDSP Synthesis tool. The resulting function occupies 12% of a XC4VSX55 device and has a 1.7 MSPS data rate.

Frequently asked questions about Arithmetic Unit IP cores

What is Multiplier Accumulator?

Multiplier Accumulator is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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