10 Bit 40 MS/s Pipeline ADC on AMS C18
The IP consists of a 10 bit 40 MS/s pipeline ADC.
- 10 Bit
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
10 Bit 40 MS/s Pipeline ADC on AMS C18
The IP consists of a 10 bit 40 MS/s pipeline ADC.
12 Bit 40 MS/s Pipeline ADC on XFAB XH018
This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling.
Integrated Photoamplifier with built-in ADC
TI-101 is an integrated circuit of XC06 HV technology.
The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches.
TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier which gain can be adjusted exter…
Fully differential RF ADC Driver
The TI-RF-DRV is a fully differential RF driver designed for differential signal processing applications.
The TI-RF-CMP is a low power RF comparator with 4 ns propagation delay designed for using in applications, where continuous-into-…
5 V Fixed Micro-power Low Dropout Linear Voltage Regulator
TI-L500 is a micro-power low dropout linear voltage regulator of XC06 HV technology.
5 MHz 14-bit 1-channel 300 kSPS cascade delta-sigma ADC
The block is fourth order cascade (2-2) delta-sigma ADC with 5-level quantizers in both stages.
14-bit, 1200 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B1P2G-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni D…
14-bit, 600 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B600M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni D…
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni D…
5 MHz 14-bit 2 channel 300 kSPS cascade delta-sigma ADC
The block is fourth order cascade (2-2) delta-sigma ADC with 5-level quantizers in both stages.
Low-Noise Bandgap Reference - Low Noise: 63nV/√Hz, PSRR: -80dB - TSMC 0.18um CMOS (CLM18)
This macro-cell is a low noise, high PSRR voltage reference core designed for TSMC 0.18um (CLM18) CMOS technology.
General Purpose PMU - Thermal shutdown and overvoltage protected - SilTerra 0.18 um
This macro-cell is a Power Management Unit (PMU) core designed for Silterra 0.18µm C18GH5 CMOS technology in TO (thick oxide) and…
Bandgap Voltage Reference - Low Integrated Noise (57.2µVrms) -TSMC 40nm
This macro-cell is a low power voltage reference generator core designed for TSMC 40nm CRN40LP CMOS technology.
16nA Resistive Current Bias Low Voltage (1.0V), Low Power (360nW @ 1.2V)
This macro-cell is a low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology.
17nA Current Bias with Enable Low Voltage (1.0V), Ultra Low Power (90nW @ 1.8V)
This macro-cell is a low power general purpose current bias generator core designed for TowerJazz 0.18µm TS18SL CMOS technology.
The CC-100 IP is a Hyper-decoupling capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity E…
2 to 27 MHz Intermediate frequency amplifier
IFA consist of 3-stages amplifier with tunable gain, AGC system, linear output buffer for differential analog output, analog-digi…