TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- G
PLL IP cores (Phase-Locked Loop IP) are essential components in modern SoC, ASIC, and mixed-signal designs, enabling precise clock generation, frequency synthesis, and jitter reduction.
Phase-locked loop IP is widely used in applications such as high-speed interfaces (SerDes, PCIe, Ethernet), wireless communication, processors, and clock distribution networks.
This page allows you to compare PLL IP cores from leading vendors by frequency range, jitter performance, power consumption, process node compatibility, and supported use cases.
Whether you need a low-power PLL for IoT or a high-performance low-jitter PLL for high-speed data links, you can quickly identify the most suitable solution for your design.
TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015LV 150nm Deskew PLL - 140MHz-700MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015G 150nm Deskew PLL - 65MHz-325MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015G 150nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
The iniADPLL is an all digital implementation of a phase locked loop.
1.056GHz Analog PLL for Spread Spectrum Clock Generator IP
1.056GHz analog phase-locked loop (PLL) IP for a spread spectrum clock generator (SSCG) using TSMC's 40nm Low Power (LP) process technology
1.25GHz Analog PLL for Frequency Multiplying IP
1.25GHz Analog PLL for Frequency Multiplying IP on TSMC 40nm LP
1.68GHz Analog PLL for Skew Adjust IP
1.68GHz Analog PLL for Skew Adjust IP on TSMC 28nm HPM/HPC
1.8GHz Analog PLL for Spread Spectrum Clock Generator IP
1.8GHz Analog PLL for Spread Spectrum Clock Generator IP on TSMC 28nm HPM/HPC
1.4GHz Analog PLL for Skew Adjust IP
1.4GHz Analog PLL for Skew Adjust IP on TSMC's 28nm HPC+
4GHz Analog PLL for Frequency Multiplying IP
Analog-PLL For Frequency Multiplying on TSMC 28nm HPC+
3GHz All-Digital PLL for Spread Spectrum Clock Generator IP
3GHz all-digital analog phase-locked loop (PLL) IP for a spread spectrum clock generator (SSCG) using TSMC's T22ULP
4.1GHz Analog PLL for Frequency Multiplying IP
4.1GHz Analog PLL for Frequency Multiplying IP on TSMC 16nm FF+